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Date: Fri, 8 Sep 2006 17:03:52 -0700
From: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
To: Christoph Lameter <clameter@sgi.com>
Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>, akpm@osdl.org,
       linux-kernel@vger.kernel.org, npiggin@suse.de, mingo@elte.hu
Subject: Re: [PATCH] Fix longstanding load balancing bug in the scheduler.
Message-ID: <20060908170352.C9446@unix-os.sc.intel.com>
References: <Pine.LNX.4.64.0609061634240.13322@schroedinger.engr.sgi.com> <20060908103529.A9121@unix-os.sc.intel.com> <Pine.LNX.4.64.0609081135590.23089@schroedinger.engr.sgi.com> <20060908130028.A9446@unix-os.sc.intel.com> <Pine.LNX.4.64.0609081316580.24016@schroedinger.engr.sgi.com>
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In-Reply-To: <Pine.LNX.4.64.0609081316580.24016@schroedinger.engr.sgi.com>; from clameter@sgi.com on Fri, Sep 08, 2006 at 01:19:28PM -0700
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On Fri, Sep 08, 2006 at 01:19:28PM -0700, Christoph Lameter wrote:
> On Fri, 8 Sep 2006, Siddha, Suresh B wrote:
> 
> > On Fri, Sep 08, 2006 at 11:40:51AM -0700, Christoph Lameter wrote:
> > > The balancing operation is not that frequent and having to treat a special 
> > > case in the callers would make code more complicated and likely offset the
> > > gains in this function.
> > 
> > This solution as such is not accurate and clean :) and my suggestion is
> > not making it any more ugly.
> > 
> > With increase in NR_CPUS, cost of cpumask operations will increase and 
> > we shouldn't penalize the other logical threads or cores sharing the caches by
> > bringing in unnecessary cache lines.
> 
> One cacheline sized 128bytes will support all 1024 cpus that IA64 allows. 
> cacheline align the cpumask?

one or more, it is unnecessary for the common case.

thanks,
suresh