Re: question regarding cacheline size

[Grant Grundler <grundler@parisc-linux.org>]

On Thu, Sep 07, 2006 at 12:04:07PM -0400, Jeff Garzik wrote:
...
> >Current API (pci_set_mwi()) ties enabling MRM/MRL with enabling MWI
> >and I don't see a really good reason for that. Only the converse
> >is true - enabling MWI requires setting cachelinesize.
> 
> Correct, that's why it was done that way, when I wrote the API. 
> Enabling MWI required making sure the BIOS configured our CLS for us, 
> which was often not the case.  No reason why we can't do a
> 
> 	pdev->set_cls = 1;
> 	rc = pci_enable_device(pdev);

I was thinking the pci_enable_device could safely set CLS if MWI
were NOT enabled. I'm sure somethings would break that worked before
but that's what quirks are for, right?

Anyway, I'm convinced the arch specific PCI code should be setting CLS
either at bus_fixup or via some quirks to compensate for "broken" firmware
(which didn't set CLS). Maybe there is more brokn HW out there than
I think...I'm easy convince that's the case.

If a driver wanted to enable MWI, then pci_set_mwi() should
verify (or force) CLS setttings or return an error.
That part seems pretty straight forward and don't need a
change in API here.

thanks,
grant