* [PATCH] [0/2] Two more x86-64 bug fixes in recent pull @ 2006-10-21 22:50 Andi Kleen 2006-10-21 22:50 ` [PATCH] [1/2] x86_64: Fix C3 timer test Andi Kleen 2006-10-21 22:50 ` [PATCH] [2/2] x86_64: increase PHB1 split transaction timeout Andi Kleen 0 siblings, 2 replies; 5+ messages in thread From: Andi Kleen @ 2006-10-21 22:50 UTC (permalink / raw) To: patches, linux-kernel Two last minute fixes. -Andi ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] [1/2] x86_64: Fix C3 timer test 2006-10-21 22:50 [PATCH] [0/2] Two more x86-64 bug fixes in recent pull Andi Kleen @ 2006-10-21 22:50 ` Andi Kleen 2006-10-21 22:50 ` [PATCH] [2/2] x86_64: increase PHB1 split transaction timeout Andi Kleen 1 sibling, 0 replies; 5+ messages in thread From: Andi Kleen @ 2006-10-21 22:50 UTC (permalink / raw) To: patches, linux-kernel There was a typo in the C3 latency test to decide of the TSC should be used or not. It used the C2 latency threshold, not the C3 one. Fix that. This should fix the time on various dual core laptops. Signed-off-by: Andi Kleen <ak@suse.de> --- arch/x86_64/kernel/time.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: linux/arch/x86_64/kernel/time.c =================================================================== --- linux.orig/arch/x86_64/kernel/time.c +++ linux/arch/x86_64/kernel/time.c @@ -948,7 +948,7 @@ __cpuinit int unsynchronized_tsc(void) if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { #ifdef CONFIG_ACPI /* But TSC doesn't tick in C3 so don't use it there */ - if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100) + if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 1000) return 1; #endif return 0; ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] [2/2] x86_64: increase PHB1 split transaction timeout 2006-10-21 22:50 [PATCH] [0/2] Two more x86-64 bug fixes in recent pull Andi Kleen 2006-10-21 22:50 ` [PATCH] [1/2] x86_64: Fix C3 timer test Andi Kleen @ 2006-10-21 22:50 ` Andi Kleen 2006-10-21 23:13 ` David Rientjes 1 sibling, 1 reply; 5+ messages in thread From: Andi Kleen @ 2006-10-21 22:50 UTC (permalink / raw) To: Muli Ben-Yehuda, patches, linux-kernel From: Muli Ben-Yehuda <muli@il.ibm.com> This patch increases the timeout for PCI split transactions on PHB1 on the first Calgary to work around an issue with the aic94xx adapter. Fixes kernel.org bugzilla #7180 (http://bugzilla.kernel.org/show_bug.cgi?id=7180) Based on excellent debugging and a patch by Darrick J. Wong <djwong@us.ibm.com> Signed-off-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Jon Mason <jdmason@kudzu.us> Signed-off-by: Andi Kleen <ak@suse.de> Acked-by: Darrick J. Wong <djwong@us.ibm.com> --- arch/x86_64/kernel/pci-calgary.c | 44 ++++++++++++++++++++++++++++++++++++++- 1 files changed, 43 insertions(+), 1 deletion(-) Index: linux/arch/x86_64/kernel/pci-calgary.c =================================================================== --- linux.orig/arch/x86_64/kernel/pci-calgary.c +++ linux/arch/x86_64/kernel/pci-calgary.c @@ -52,7 +52,8 @@ #define ONE_BASED_CHASSIS_NUM 1 /* register offsets inside the host bridge space */ -#define PHB_CSR_OFFSET 0x0110 +#define CALGARY_CONFIG_REG 0x0108 +#define PHB_CSR_OFFSET 0x0110 /* Channel Status */ #define PHB_PLSSR_OFFSET 0x0120 #define PHB_CONFIG_RW_OFFSET 0x0160 #define PHB_IOBASE_BAR_LOW 0x0170 @@ -83,6 +84,8 @@ #define TAR_VALID 0x0000000000000008UL /* CSR (Channel/DMA Status Register) */ #define CSR_AGENT_MASK 0xffe0ffff +/* CCR (Calgary Configuration Register) */ +#define CCR_2SEC_TIMEOUT 0x000000000000000EUL #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ #define MAX_NUM_CHASSIS 8 /* max number of chassis */ @@ -732,6 +735,38 @@ static void calgary_watchdog(unsigned lo } } +static void __init calgary_increase_split_completion_timeout(void __iomem *bbar, + unsigned char busnum) +{ + u64 val64; + void __iomem *target; + unsigned long phb_shift = -1; + u64 mask; + + switch (busno_to_phbid(busnum)) { + case 0: phb_shift = (63 - 19); + break; + case 1: phb_shift = (63 - 23); + break; + case 2: phb_shift = (63 - 27); + break; + case 3: phb_shift = (63 - 35); + break; + default: + BUG_ON(busno_to_phbid(busnum)); + } + + target = calgary_reg(bbar, CALGARY_CONFIG_REG); + val64 = be64_to_cpu(readq(target)); + + /* zero out this PHB's timer bits */ + mask = ~(0xFUL << phb_shift); + val64 &= mask; + val64 |= (CCR_2SEC_TIMEOUT << phb_shift); + writeq(cpu_to_be64(val64), target); + readq(target); /* flush */ +} + static void __init calgary_enable_translation(struct pci_dev *dev) { u32 val32; @@ -756,6 +791,13 @@ static void __init calgary_enable_transl writel(cpu_to_be32(val32), target); readl(target); /* flush */ + /* + * Give split completion a longer timeout on bus 1 for aic94xx + * http://bugzilla.kernel.org/show_bug.cgi?id=7180 + */ + if (busnum == 1) + calgary_increase_split_completion_timeout(bbar, busnum); + init_timer(&tbl->watchdog_timer); tbl->watchdog_timer.function = &calgary_watchdog; tbl->watchdog_timer.data = (unsigned long)dev; ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] [2/2] x86_64: increase PHB1 split transaction timeout 2006-10-21 22:50 ` [PATCH] [2/2] x86_64: increase PHB1 split transaction timeout Andi Kleen @ 2006-10-21 23:13 ` David Rientjes 2006-10-22 1:53 ` Muli Ben-Yehuda 0 siblings, 1 reply; 5+ messages in thread From: David Rientjes @ 2006-10-21 23:13 UTC (permalink / raw) To: Andi Kleen; +Cc: Muli Ben-Yehuda, patches, linux-kernel On Sun, 22 Oct 2006, Andi Kleen wrote: > Index: linux/arch/x86_64/kernel/pci-calgary.c > =================================================================== > --- linux.orig/arch/x86_64/kernel/pci-calgary.c > +++ linux/arch/x86_64/kernel/pci-calgary.c > @@ -52,7 +52,8 @@ > #define ONE_BASED_CHASSIS_NUM 1 > > /* register offsets inside the host bridge space */ > -#define PHB_CSR_OFFSET 0x0110 > +#define CALGARY_CONFIG_REG 0x0108 > +#define PHB_CSR_OFFSET 0x0110 /* Channel Status */ > #define PHB_PLSSR_OFFSET 0x0120 > #define PHB_CONFIG_RW_OFFSET 0x0160 > #define PHB_IOBASE_BAR_LOW 0x0170 > @@ -83,6 +84,8 @@ > #define TAR_VALID 0x0000000000000008UL > /* CSR (Channel/DMA Status Register) */ > #define CSR_AGENT_MASK 0xffe0ffff > +/* CCR (Calgary Configuration Register) */ > +#define CCR_2SEC_TIMEOUT 0x000000000000000EUL > > #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ > #define MAX_NUM_CHASSIS 8 /* max number of chassis */ > @@ -732,6 +735,38 @@ static void calgary_watchdog(unsigned lo > } > } > > +static void __init calgary_increase_split_completion_timeout(void __iomem *bbar, > + unsigned char busnum) > +{ > + u64 val64; > + void __iomem *target; > + unsigned long phb_shift = -1; The initialization of this to -1 is unclear to me since we fall through to BUG_ON() if busno_to_phbid() returns anything under than 0-3. A shift value of MAX_ULONG is never appropriate. > + u64 mask; > + > + switch (busno_to_phbid(busnum)) { > + case 0: phb_shift = (63 - 19); > + break; > + case 1: phb_shift = (63 - 23); > + break; > + case 2: phb_shift = (63 - 27); > + break; > + case 3: phb_shift = (63 - 35); > + break; > + default: > + BUG_ON(busno_to_phbid(busnum)); > + } > + > + target = calgary_reg(bbar, CALGARY_CONFIG_REG); > + val64 = be64_to_cpu(readq(target)); > + > + /* zero out this PHB's timer bits */ > + mask = ~(0xFUL << phb_shift); > + val64 &= mask; > + val64 |= (CCR_2SEC_TIMEOUT << phb_shift); > + writeq(cpu_to_be64(val64), target); > + readq(target); /* flush */ > +} > + > static void __init calgary_enable_translation(struct pci_dev *dev) > { > u32 val32; > @@ -756,6 +791,13 @@ static void __init calgary_enable_transl > writel(cpu_to_be32(val32), target); > readl(target); /* flush */ > > + /* > + * Give split completion a longer timeout on bus 1 for aic94xx > + * http://bugzilla.kernel.org/show_bug.cgi?id=7180 > + */ > + if (busnum == 1) > + calgary_increase_split_completion_timeout(bbar, busnum); > + > init_timer(&tbl->watchdog_timer); > tbl->watchdog_timer.function = &calgary_watchdog; > tbl->watchdog_timer.data = (unsigned long)dev; > - > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] [2/2] x86_64: increase PHB1 split transaction timeout 2006-10-21 23:13 ` David Rientjes @ 2006-10-22 1:53 ` Muli Ben-Yehuda 0 siblings, 0 replies; 5+ messages in thread From: Muli Ben-Yehuda @ 2006-10-22 1:53 UTC (permalink / raw) To: David Rientjes; +Cc: Andi Kleen, patches, linux-kernel On Sat, Oct 21, 2006 at 04:13:28PM -0700, David Rientjes wrote: > > +static void __init calgary_increase_split_completion_timeout(void __iomem *bbar, > > + unsigned char busnum) > > +{ > > + u64 val64; > > + void __iomem *target; > > + unsigned long phb_shift = -1; > > The initialization of this to -1 is unclear to me since we fall through to > BUG_ON() if busno_to_phbid() returns anything under than 0-3. A shift > value of MAX_ULONG is never appropriate. Without the initialization gcc warns about 'phb_shift' potentially being used unitialized. I used '-1' exactly because it is never appropriate. Cheers, Muli ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2006-10-22 1:53 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2006-10-21 22:50 [PATCH] [0/2] Two more x86-64 bug fixes in recent pull Andi Kleen 2006-10-21 22:50 ` [PATCH] [1/2] x86_64: Fix C3 timer test Andi Kleen 2006-10-21 22:50 ` [PATCH] [2/2] x86_64: increase PHB1 split transaction timeout Andi Kleen 2006-10-21 23:13 ` David Rientjes 2006-10-22 1:53 ` Muli Ben-Yehuda
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