Re: Ordering between PCI config space writes and MMIO reads?

[David Miller <davem@davemloft.net>]

From: Matthew Wilcox <matthew@wil.cx>
Date: Tue, 24 Oct 2006 16:36:32 -0600

> This is only really a problem for setup (when we program the BARs), so
> it seems silly to enforce an ordering at any other time.  Reluctantly, I
> must disagree with Jeff -- drivers need to fix this.

One thing is that we definitely don't want to fix this by,
for example, reading back the PCI_COMMAND register or something
like that.  That causes two problems:

1) Some PCI config writes shut the device down and make it
   no respond to some kinds of PCI config transactions.
   One example is putting the device into D3 or similar
   power state, another is performing a device reset.

2) Several drivers use PCI config space accesses to touch the
   main registers in order to workaround bugs in the PCI-X
   implementation of their chip or similar (tg3 has a few
   cases like this), doing a PCI config space readback will
   kill performance quite a bit for an already slow situation.

In fact, I do recall that one of the x86 PCI config space access
implementations did a readback like this, and we had to remove
it because it caused problems when doing a reset on tg3 chips
when using PCI config space register write to do the reset.