From: Andi Kleen <ak@suse.de>
To: thockin@hockin.org
Cc: Andrew Morton <akpm@osdl.org>,
Sergio Monteiro Basto <sergio@sergiomb.no-ip.org>,
Lee Revell <rlrevell@joe-job.com>,
Chris Friesen <cfriesen@nortel.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
john stultz <johnstul@us.ibm.com>
Subject: Re: AMD X2 unsynced TSC fix?
Date: Sat, 28 Oct 2006 02:46:41 -0700 [thread overview]
Message-ID: <200610280246.42384.ak@suse.de> (raw)
In-Reply-To: <20061028064924.GA9127@hockin.org>
> Nothing at all, or just the the low few bits are writeable? I had heard,
> but never seen that some Intel CPUs only allowed 16 bits of writable bits
> in the TSC MSR. I also heard of, but never saw, CPUs that cleared the TSC
> to 0 on a write!
Normally on Intel you can only write the first 32bits
-Andi
next prev parent reply other threads:[~2006-10-28 9:52 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-10-27 17:15 AMD X2 unsynced TSC fix? Lee Revell
2006-10-27 20:18 ` Luca Tettamanti
2006-10-27 23:04 ` thockin
2006-10-28 0:00 ` Luca Tettamanti
2006-10-28 0:17 ` Lee Revell
2006-10-28 2:46 ` thockin
2006-10-28 3:59 ` Andi Kleen
2006-10-28 6:32 ` thockin
2006-10-28 9:14 ` Vojtech Pavlik
2006-10-28 18:22 ` Lee Revell
2006-10-28 19:57 ` Vojtech Pavlik
2006-10-28 22:54 ` thockin
2006-10-28 1:04 ` Andi Kleen
2006-10-28 3:28 ` Lee Revell
2006-10-28 5:28 ` Willy Tarreau
2006-10-28 18:08 ` Lee Revell
2006-10-28 19:14 ` thockin
2006-10-30 17:22 ` Langsdorf, Mark
2006-10-28 18:37 ` Andi Kleen
2006-10-28 19:15 ` Willy Tarreau
2006-10-28 19:18 ` thockin
2006-10-28 19:32 ` Willy Tarreau
2006-10-28 19:42 ` thockin
2006-10-28 20:16 ` Willy Tarreau
2006-10-28 19:33 ` Andi Kleen
2006-10-28 20:04 ` Willy Tarreau
2006-10-28 20:11 ` Andi Kleen
2006-10-28 20:36 ` Willy Tarreau
2006-10-29 1:28 ` Lee Revell
2006-10-28 21:00 ` Lee Revell
2006-10-31 11:12 ` Pádraig Brady
2006-10-31 15:31 ` Willy Tarreau
2006-10-30 20:30 ` Christoph Lameter
2006-10-27 20:35 ` Andi Kleen
2006-10-27 20:41 ` Lee Revell
2006-10-27 21:48 ` Chris Friesen
2006-10-27 22:08 ` Lee Revell
2006-10-28 3:58 ` Sergio Monteiro Basto
2006-10-28 4:06 ` Andi Kleen
2006-10-28 4:22 ` Sergio Monteiro Basto
2006-10-30 3:10 ` Sergio Monteiro Basto
2006-10-30 15:23 ` Andi Kleen
[not found] ` <1162253008.2999.9.camel@localhost.portugal>
2006-10-31 0:14 ` Lee Revell
2006-10-31 0:25 ` john stultz
2006-10-31 2:41 ` Siddha, Suresh B
2006-10-31 15:05 ` Sergio Monteiro Basto
2006-11-01 1:46 ` Sergio Monteiro Basto
2006-11-01 2:44 ` Siddha, Suresh B
2006-11-08 0:22 ` Sergio Monteiro Basto
2006-11-08 19:53 ` Thomas Gleixner
2006-11-09 0:39 ` Sergio Monteiro Basto
2006-11-09 1:13 ` john stultz
2006-11-09 1:27 ` Sergio Monteiro Basto
2006-11-15 1:51 ` Sergio Monteiro Basto
[not found] ` <20061115193514.41C01102C011@mail.goron.de>
2006-11-16 1:38 ` Sergio Monteiro Basto
2006-11-16 1:45 ` Sergio Monteiro Basto
2006-10-28 6:35 ` thockin
2006-10-28 6:46 ` Andrew Morton
2006-10-28 6:49 ` thockin
2006-10-28 7:13 ` Andrew Morton
2006-10-28 7:25 ` thockin
2006-10-28 9:46 ` Andi Kleen [this message]
2006-10-28 9:45 ` Andi Kleen
2006-10-28 9:48 ` Andi Kleen
2006-10-27 21:58 ` Friedrich Göpel
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