MIPS atomic operations, "sync"

MIPS atomic operations, "sync"

[Mathieu Desnoyers]

Hi,

I am currently creating a "LOCK" prefix free and memory barrier free version
of atomic.h to fulfill my tracer (LTTng) needs, which is to atomically update
per-cpu data and have a minimal performance loss.

I just came across the MIPS atomic.h and system.h implementations in 2.6.18
which brings a question :

Why are the primitives in include/asm-mips/atomic.h using the "sync"
instruction even in the UP case ? system.h cmpxchg only uses the sync in the
SMP case.

Mathieu


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Re: MIPS atomic operations, "sync"

[Ralf Baechle]

On Fri, Nov 10, 2006 at 01:40:49PM -0500, Mathieu Desnoyers wrote:

> I am currently creating a "LOCK" prefix free and memory barrier free version
> of atomic.h to fulfill my tracer (LTTng) needs, which is to atomically update
> per-cpu data and have a minimal performance loss.
> 
> I just came across the MIPS atomic.h and system.h implementations in 2.6.18
> which brings a question :
> 
> Why are the primitives in include/asm-mips/atomic.h using the "sync"
> instruction even in the UP case ? system.h cmpxchg only uses the sync in the
> SMP case.

Why are the standard atomic operations insufficient for your needs?

There is an enormous amout of subtilities in those atomic ops for some
architectures you probably do yourself a big favor by avoiding new
variants.

  Ralf

Re: MIPS atomic operations, "sync"

[Mathieu Desnoyers]

* Ralf Baechle (ralf@linux-mips.org) wrote:
> On Fri, Nov 10, 2006 at 01:40:49PM -0500, Mathieu Desnoyers wrote:
> 
> > I am currently creating a "LOCK" prefix free and memory barrier free version
> > of atomic.h to fulfill my tracer (LTTng) needs, which is to atomically update
> > per-cpu data and have a minimal performance loss.
> > 
> > I just came across the MIPS atomic.h and system.h implementations in 2.6.18
> > which brings a question :
> > 
> > Why are the primitives in include/asm-mips/atomic.h using the "sync"
> > instruction even in the UP case ? system.h cmpxchg only uses the sync in the
> > SMP case.
> 
> Why are the standard atomic operations insufficient for your needs?
> 
> There is an enormous amout of subtilities in those atomic ops for some
> architectures you probably do yourself a big favor by avoiding new
> variants.
> 

Performance cost.

I add a memory barrier where needed when the data needs to appear to be written
sequentially from the other CPUs perspective.

Mathieu


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