From: Andi Kleen <ak@suse.de>
To: eranian@hpl.hp.com
Cc: Jeremy Fitzhardinge <jeremy@goop.org>,
linux-kernel@vger.kernel.org, akpm@osdl.org
Subject: Re: [PATCH] i386 add Intel PEBS and BTS cpufeature bits and detection
Date: Fri, 17 Nov 2006 10:22:20 +0100 [thread overview]
Message-ID: <200611171022.20708.ak@suse.de> (raw)
In-Reply-To: <20061117075750.GA19907@frankl.hpl.hp.com>
> The former
> stores from/to information into MSRs and is very small (4 branches).
P4 since Prescott has 16
> On recent processors LBR and BTS can be constrained by priv level.
Doesn't help for kernel debugging.
-Andi
next prev parent reply other threads:[~2006-11-17 9:22 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-11-15 21:32 [PATCH] i386 add Intel PEBS and BTS cpufeature bits and detection Stephane Eranian
2006-11-15 21:34 ` [PATCH] x86-64 " Stephane Eranian
2006-11-16 0:18 ` [PATCH] i386 " Andrew Morton
2006-11-16 14:20 ` [PATCH] x86-64 add Intel BTS cpufeature bit and detection (take 2) Stephane Eranian
2006-11-16 14:22 ` [PATCH] i386 " Stephane Eranian
2006-11-16 14:23 ` [PATCH] x86-64 " Andi Kleen
2006-11-17 1:34 ` [PATCH] i386 add Intel PEBS and BTS cpufeature bits and detection Jeremy Fitzhardinge
2006-11-17 4:29 ` Andi Kleen
2006-11-17 7:57 ` Stephane Eranian
2006-11-17 9:22 ` Andi Kleen [this message]
2006-11-17 12:29 ` Stephane Eranian
2006-11-17 22:57 ` Jeremy Fitzhardinge
2006-11-18 8:24 ` Andi Kleen
2006-11-23 6:03 ` Keith Owens
2006-11-23 8:52 ` Andi Kleen
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