Re: Running Linux on FPGA

Re: Running Linux on FPGA

[Ralf Baechle]

On Sat, Jan 20, 2007 at 11:42:37PM +0000, sathesh babu wrote:

> Hi,
>   I am trying to run Linux-2.6.18.2 ( with preemption enable) kernel on FPGA board which has MIPS24KE processor runs at 12 MHZ. Programmed the timer to give interrupt at every 10msec.
>   I am seeing some inconsistence behavior during boot up processor. Some times it stops after "NET: Registered protocol family 17" and "VFS: Mounted root (jffs2 filesystem).".
>   Could some give some pointers why the behavior is random.
>   Is it OK to program the timer to 10 msec? or should it be more.

The overhead of timer interrupts at this low clockrate is significant
so I recommend to minimize the timer interrupt rate as far as possible.
This is really a tradeoff between latency and overhead and matters
much less on hardcores which run at hundreds of MHz.  For power sensitive
applications lowering the interrupt rate can also help.  And that's alredy
pretty much what you need to know, that is a 10ms  timer is fine.

Btw, is this coincidentally on a CoreFPGA 2 or 3 CPU card on a Malta board?

  Ralf

Re: Running Linux on FPGA

[Sunil Naidu]

On 1/21/07, Ralf Baechle <ralf@linux-mips.org> wrote:
>
> The overhead of timer interrupts at this low clockrate is significant
> so I recommend to minimize the timer interrupt rate as far as possible.
> This is really a tradeoff between latency and overhead and matters
> much less on hardcores which run at hundreds of MHz.  For power sensitive
> applications lowering the interrupt rate can also help.  And that's alredy
> pretty much what you need to know, that is a 10ms  timer is fine.
>

I have worked with FPGA Linux system which is reconfigurable
on-the-fly by the 200Mhz ARM9 CPU running Debian Linux, Altera Cyclone
II FPGA is included on my TS-7300 board. Advantage is, Altera FPGA and
a dedicated high-speed bus between the CPU and FPGA provides a good
design scope to provide many solutions.

Coming to boot up (by an USB 1GB SD card), by doing enough software
tuning bootup to a Linux prompt takes just 1.69 seconds after
power-up. If I remember correctly, SD image will look at the state of
jumper 6 (should be put ON), the full Debian bootup will be bypassed
and the system will instead drop straight to a shell prompt. 1.69
seconds after power-on the serial console prompt is active and 2.41
seconds after power-on the video console is displayed.

This software is based on Debian & has a vendor supplied Linux boot
loader. Currently am working (slowly in free time) to bring the whole
thing to FC6.  Shall post the progres...

>
>   Ralf

~Akula2

Re: Running Linux on FPGA

[Kevin D. Kissell]

> > The overhead of timer interrupts at this low clockrate is significant
> > so I recommend to minimize the timer interrupt rate as far as possible.
> > This is really a tradeoff between latency and overhead and matters
> > much less on hardcores which run at hundreds of MHz.  For power sensitive
> > applications lowering the interrupt rate can also help.  And that's alredy
> > pretty much what you need to know, that is a 10ms  timer is fine.
> >
> 
> I have worked with FPGA Linux system which is reconfigurable
> on-the-fly by the 200Mhz ARM9 CPU running Debian Linux, Altera Cyclone
> II FPGA is included on my TS-7300 board. Advantage is, Altera FPGA and
> a dedicated high-speed bus between the CPU and FPGA provides a good
> design scope to provide many solutions.

What's your point here?  A 200MHz hard ore won't see the issues 
under discussion.  We're talking about systems where the CPU itself
is "soft" and implemented in an FPGA.

            Regards,

            Kevin K.

Re: Running Linux on FPGA

[Jan Engelhardt]

On Jan 21 2007 00:14, Ralf Baechle wrote:
>On Sat, Jan 20, 2007 at 11:42:37PM +0000, sathesh babu wrote:
>
>>   I am trying to run Linux-2.6.18.2 ( with preemption enable)
>>   kernel on FPGA board which has MIPS24KE processor runs at 12
>>   MHZ. Programmed the timer to give interrupt at every 10msec. I
>>   am seeing some inconsistence behavior during boot up processor.
>>   Some times it stops after "NET: Registered protocol family 17"
>>   and "VFS: Mounted root (jffs2 filesystem).". Could some give
>>   some pointers why the behavior is random. Is it OK to program
>>   the timer to 10 msec? or should it be more.
>
>The overhead of timer interrupts at this low clockrate is
>significant so I recommend to minimize the timer interrupt rate as
>far as possible. This is really a tradeoff between latency and
>overhead and matters much less on hardcores which run at hundreds of
>MHz.

Hm I've been running 2.6.13 on a 10/20 MHz (switchable) i386 @ 100 Hz
before without any hangs during boot or operation.


	-`J'
-- 

Re: Running Linux on FPGA

[Kevin D. Kissell]

> On Jan 21 2007 00:14, Ralf Baechle wrote:
> >On Sat, Jan 20, 2007 at 11:42:37PM +0000, sathesh babu wrote:
> >
> >>   I am trying to run Linux-2.6.18.2 ( with preemption enable)
> >>   kernel on FPGA board which has MIPS24KE processor runs at 12
> >>   MHZ. Programmed the timer to give interrupt at every 10msec. I
> >>   am seeing some inconsistence behavior during boot up processor.
> >>   Some times it stops after "NET: Registered protocol family 17"
> >>   and "VFS: Mounted root (jffs2 filesystem).". Could some give
> >>   some pointers why the behavior is random. Is it OK to program
> >>   the timer to 10 msec? or should it be more.
> >
> >The overhead of timer interrupts at this low clockrate is
> >significant so I recommend to minimize the timer interrupt rate as
> >far as possible. This is really a tradeoff between latency and
> >overhead and matters much less on hardcores which run at hundreds of
> >MHz.
> 
> Hm I've been running 2.6.13 on a 10/20 MHz (switchable) i386 @ 100 Hz
> before without any hangs during boot or operation.

Interrupt service overhead varies a bit between architectures, but your
observation isn't too surprising.  While the 1000Hz Linux 2.6 default
is just bad craziness for embedded cores and FPGA prototypes, I've
only seen 100Hz be truly unusable for sub-megahertz hardware simulators,
and then only when running virtual SMP kernels, where multiple virtual
"CPUs" on the same core all had to perform timer interrupt service
every clock interval, which multiplies the proportion of available cycles
consumed.  But even if the system boots and runs, it's pretty scary
to look at the proportion of time that a 20MHz core spends in interrupt
service with a HZ value of 100 or more.

So on one hand I agree with Ralf that on slow systems, especially
FPGA systems, one wants to keep the clock interrupt frequency
down to no more than 100Hz as a general rule (less than 100
wouldn't compile on 2.6.9 without some minor patches, which
took the minimum down to HZ=48, below which the various macros
that depend on HZ start generating divide-by-zero problems),
while on the other hand I agree with Jan that it's by no means certain
that Satesh's problem is really one of too many clock interrupts.

            Regards,

            Kevin K.