Re: [PATCH 2.6.21-rc5] Flush MSI-X table writes (rev 3)

[Greg KH <gregkh@suse.de>]

On Fri, Mar 30, 2007 at 12:47:47PM -0700, Andrew Morton wrote:
> On Fri, 30 Mar 2007 13:04:02 -0600
> ebiederm@xmission.com (Eric W. Biederman) wrote:
> 
> > Mitch Williams <mitch.a.williams@intel.com> writes:
> > 
> > > This patch fixes a kernel bug which is triggered when using the
> > > irqbalance daemon with MSI-X hardware.
> > >
> > > Because both MSI-X interrupt messages and MSI-X table writes are posted,
> > > it's possible for them to cross while in-flight.  This results in
> > > interrupts being received long after the kernel thinks they're disabled,
> > > and in interrupts being sent to stale vectors after rebalancing.
> > >
> > > This patch performs a read flush after writes to the MSI-X table for
> > > mask and unmask operations.  Since the SMP affinity is set while
> > > the interrupt is masked, and since it's unmasked immediately after,
> > > no additional flushes are required in the various affinity setting
> > > routines.
> > >
> > > This patch has been validated with (unreleased) network hardware which
> > > uses MSI-X.
> > >
> > > Revised with input from Eric Biederman.
> > 
> > Acked-by: "Eric W. Biederman" <ebiederm@xmission.com>
> 
> Did we end up deciding whether this is (needed*safe) enough for 2.6.21?

I say no for now, I have seen no bug reports for any hardware that is
not in a lab for this.

thanks,

greg k-h