[PATCH] PCI mmconfig support for Intel 915 bridges

[PATCH] PCI mmconfig support for Intel 915 bridges

[Jesse Barnes]

This is a resend of the patch I sent earlier to Oliver.  It adds support
for Intel 915 bridge chips to the new PCI MMConfig detection code.  Tested
and works on my sole 915 based platform (a Toshiba laptop).  I added
register masking per Oliver's suggestion, and moved the __init qualifier to
after the 'static const char' to match Ogawa-san's recent cleanup patches.

Over time we can probably associate more PCI IDs with this routine, since
i915 family contains a few other chips.  But since I didn't have platforms
to test such additions on, they're left out for now.

Signed-off-by:  Jesse Barnes <jbarnes@virtuousgeek.org>

Thanks,
Jesse

diff -Napur -X /home/jbarnes/dontdiff linux-2.6.19-mmconfig.orig/arch/i386/pci/mmconfig-shared.c linux-2.6.19-mmconfig/arch/i386/pci/mmconfig-shared.c
--- linux-2.6.19-mmconfig.orig/arch/i386/pci/mmconfig-shared.c	2007-01-07 10:10:29.000000000 -0800
+++ linux-2.6.19-mmconfig/arch/i386/pci/mmconfig-shared.c	2007-01-10 18:46:46.000000000 -0800
@@ -71,6 +71,26 @@ static __init const char *pci_mmcfg_e752
 	return "Intel Corporation E7520 Memory Controller Hub";
 }
 
+static const char __init *pci_mmcfg_intel_915(void)
+{
+	u32 pciexbar, len = 0;
+
+	pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);
+
+	/* No enable bit or size field, so assume 256M range is enabled. */
+	len = 0x10000000U;
+	pci_mmcfg_config_num = 1;
+	pciexbar &= 0xe0000000; /* mask out potentially bogus bits */
+
+	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
+	pci_mmcfg_config[0].base_address = pciexbar;
+	pci_mmcfg_config[0].pci_segment_group_number = 0;
+	pci_mmcfg_config[0].start_bus_number = 0;
+	pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
+
+	return "Intel Corporation 915PM/GM/GMS Express Memory Controller Hub";
+}
+
 static __init const char *pci_mmcfg_intel_945(void)
 {
 	u32 pciexbar, mask = 0, len = 0;
@@ -126,6 +146,7 @@ struct pci_mmcfg_hostbridge_probe {
 
 static __initdata struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] = {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, pci_mmcfg_intel_915 },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
 };
 

Re: [PATCH] PCI mmconfig support for Intel 915 bridges

[Olivier Galibert]

On Wed, Jan 10, 2007 at 06:53:03PM -0800, Jesse Barnes wrote:
> This is a resend of the patch I sent earlier to Oliver.  It adds support
> for Intel 915 bridge chips to the new PCI MMConfig detection code.  Tested
> and works on my sole 915 based platform (a Toshiba laptop).  I added
> register masking per Oliver's suggestion, and moved the __init qualifier to
> after the 'static const char' to match Ogawa-san's recent cleanup patches.
> 
> Over time we can probably associate more PCI IDs with this routine, since
> i915 family contains a few other chips.  But since I didn't have platforms
> to test such additions on, they're left out for now.
> 
> Signed-off-by:  Jesse Barnes <jbarnes@virtuousgeek.org>

Signed-off-by: Olivier Galibert <galibert@pobox.com>

Andrew, you sent me a series of emails to tell me the patches had
moved to another subsystem tree, can you tell me which one?  There is
at least an anti-regression patch to add on top (the Asus/Nvidia
special case is causing oopses right now).

  OG.

Re: [PATCH] PCI mmconfig support for Intel 915 bridges

[Jesse Barnes]

I see the other mmconfig stuff is upstream now, can we get this added 
too?  The Asus bug Olivier mentioned also appears to be fixed, so this 
patch should be safe.

Thanks,
Jesse

On Wednesday, January 10, 2007 6:53 pm Jesse Barnes wrote:
> This is a resend of the patch I sent earlier to Oliver.  It adds
> support for Intel 915 bridge chips to the new PCI MMConfig detection
> code.  Tested and works on my sole 915 based platform (a Toshiba
> laptop).  I added register masking per Oliver's suggestion, and moved
> the __init qualifier to after the 'static const char' to match
> Ogawa-san's recent cleanup patches.
>
> Over time we can probably associate more PCI IDs with this routine,
> since i915 family contains a few other chips.  But since I didn't
> have platforms to test such additions on, they're left out for now.
>
> Signed-off-by:  Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Thanks,
> Jesse
>
> diff -Napur -X /home/jbarnes/dontdiff
> linux-2.6.19-mmconfig.orig/arch/i386/pci/mmconfig-shared.c
> linux-2.6.19-mmconfig/arch/i386/pci/mmconfig-shared.c ---
> linux-2.6.19-mmconfig.orig/arch/i386/pci/mmconfig-shared.c	2007-01-07
> 10:10:29.000000000 -0800 +++
> linux-2.6.19-mmconfig/arch/i386/pci/mmconfig-shared.c	2007-01-10
> 18:46:46.000000000 -0800 @@ -71,6 +71,26 @@ static __init const char
> *pci_mmcfg_e752
>  	return "Intel Corporation E7520 Memory Controller Hub";
>  }
>
> +static const char __init *pci_mmcfg_intel_915(void)
> +{
> +	u32 pciexbar, len = 0;
> +
> +	pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);
> +
> +	/* No enable bit or size field, so assume 256M range is enabled. */
> +	len = 0x10000000U;
> +	pci_mmcfg_config_num = 1;
> +	pciexbar &= 0xe0000000; /* mask out potentially bogus bits */
> +
> +	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]),
> GFP_KERNEL); +	pci_mmcfg_config[0].base_address = pciexbar;
> +	pci_mmcfg_config[0].pci_segment_group_number = 0;
> +	pci_mmcfg_config[0].start_bus_number = 0;
> +	pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
> +
> +	return "Intel Corporation 915PM/GM/GMS Express Memory Controller
> Hub"; +}
> +
>  static __init const char *pci_mmcfg_intel_945(void)
>  {
>  	u32 pciexbar, mask = 0, len = 0;
> @@ -126,6 +146,7 @@ struct pci_mmcfg_hostbridge_probe {
>
>  static __initdata struct pci_mmcfg_hostbridge_probe
> pci_mmcfg_probes[] = { { PCI_VENDOR_ID_INTEL,
> PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, +	{
> PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB,
> pci_mmcfg_intel_915 }, { PCI_VENDOR_ID_INTEL,
> PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, };
>
> -
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Re: [PATCH] PCI mmconfig support for Intel 915 bridges

[Andrew Morton]

On Wed, 25 Apr 2007 15:35:15 -0700 Jesse Barnes <jesse.barnes@intel.com> wrote:

> I see the other mmconfig stuff is upstream now, can we get this added 
> too?  The Asus bug Olivier mentioned also appears to be fixed, so this 
> patch should be safe.
> 
> Thanks,
> Jesse

  ^^^^^ is an evil top-poster!

> 
> On Wednesday, January 10, 2007 6:53 pm Jesse Barnes wrote:
> > This is a resend of the patch I sent earlier to Oliver.  It adds
> > support for Intel 915 bridge chips to the new PCI MMConfig detection
> > code.  Tested and works on my sole 915 based platform (a Toshiba
> > laptop).  I added register masking per Oliver's suggestion, and moved
> > the __init qualifier to after the 'static const char' to match
> > Ogawa-san's recent cleanup patches.
> >
> > Over time we can probably associate more PCI IDs with this routine,
> > since i915 family contains a few other chips.  But since I didn't
> > have platforms to test such additions on, they're left out for now.
> >
> > Signed-off-by:  Jesse Barnes <jbarnes@virtuousgeek.org>
> >

Can we have a refresh, retest and resend please?

Re: [PATCH] PCI mmconfig support for Intel 915 bridges

[Jesse Barnes]

Keep reading... 

On Wednesday, April 25, 2007 4:07 pm Andrew Morton wrote:
> On Wed, 25 Apr 2007 15:35:15 -0700 Jesse Barnes 
<jesse.barnes@intel.com> wrote:
> > I see the other mmconfig stuff is upstream now, can we get this
> > added too?  The Asus bug Olivier mentioned also appears to be
> > fixed, so this patch should be safe.
> >
> > Thanks,
> > Jesse
>
>   ^^^^^ is an evil top-poster!

Hey I wanted to let you see the original! :)

> > On Wednesday, January 10, 2007 6:53 pm Jesse Barnes wrote:
> > > This is a resend of the patch I sent earlier to Oliver.  It adds
> > > support for Intel 915 bridge chips to the new PCI MMConfig
> > > detection code.  Tested and works on my sole 915 based platform
> > > (a Toshiba laptop).  I added register masking per Oliver's
> > > suggestion, and moved the __init qualifier to after the 'static
> > > const char' to match Ogawa-san's recent cleanup patches.
> > >
> > > Over time we can probably associate more PCI IDs with this
> > > routine, since i915 family contains a few other chips.  But since
> > > I didn't have platforms to test such additions on, they're left
> > > out for now.
> > >
> > > Signed-off-by:  Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Can we have a refresh, retest and resend please?

Sure.  I'll try to resend tomorrow or so.

Thanks,
Jesse