Re: [PATCH 0/2] PCI-X/PCI-Express read control interfaces - Patch correction

["Peter Oruba" <peter.oruba@amd.com>]

Am Dienstag, 15. Mai 2007 23:35:31 schrieb Andrew Vasquez:

> In general, if PCI-[Xe] capability structure exists do set-
> mmrbc()/readrq(), yet each of those pre-condition checks are already
> present in the pcix_set_mmrbc() and pcie_set_readrq().
> 
> At least for the qla2xxx case, the patch could easily distill down from:
> 
> 	...
> 	/* PCIe -- adjust Maximum Read Request Size (2048). */
> 	pcie_dctl_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
> 	if (pcie_dctl_reg)
> 		if (pcie_set_readrq(ha->pdev, 2048))
> 			DEBUG2(printk("Couldn't write PCI Express read request\n"));
> 
> to:
> 
> 	...
> 	pcie_set_readrq(ha->pdev, 2048);
> 
> 
> Whatever the decision, I can fold this into my next patchset for
> qla2xxx and submit.
> 
> 
> 

Sorry, I missed out an essential part in the qla2xxx driver, namely the MMRBC configuration for PCI-X. The submitted patch only did that for PCIe. This is the corrected version

The pre-condition check is there to not blindly call the mmrbc-functions, but to check for the bus type first. Indeed, the first patch version made this check look unnecessary.

Signed-off by: Peter Oruba <peter.oruba@amd.com>
Based on patch set by Stephen Hemminger <shemminger@linux-foundation.org>

---
--- linux-2.6.22-rc1.orig/drivers/scsi/qla2xxx/qla_init.c       2007-05-14 11:29:41.561311000 +0200
+++ linux-2.6.22-rc1/drivers/scsi/qla2xxx/qla_init.c    2007-05-16 16:08:47.811810000 +0200
@@ -269,27 +269,15 @@ qla24xx_pci_config(scsi_qla_host_t *ha)

        /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
        pcix_cmd_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX);
-       if (pcix_cmd_reg) {
-               uint16_t pcix_cmd;
-
-               pcix_cmd_reg += PCI_X_CMD;
-               pci_read_config_word(ha->pdev, pcix_cmd_reg, &pcix_cmd);
-               pcix_cmd &= ~PCI_X_CMD_MAX_READ;
-               pcix_cmd |= 0x0008;
-               pci_write_config_word(ha->pdev, pcix_cmd_reg, pcix_cmd);
-       }
+       if (pcix_cmd_reg)
+               if (pcix_set_mmrbc(ha->pdev, 2048))
+                       DEBUG2(printk("Couldn't write PCI-X read request\n"));

        /* PCIe -- adjust Maximum Read Request Size (2048). */
        pcie_dctl_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
-       if (pcie_dctl_reg) {
-               uint16_t pcie_dctl;
-
-               pcie_dctl_reg += PCI_EXP_DEVCTL;
-               pci_read_config_word(ha->pdev, pcie_dctl_reg, &pcie_dctl);
-               pcie_dctl &= ~PCI_EXP_DEVCTL_READRQ;
-               pcie_dctl |= 0x4000;
-               pci_write_config_word(ha->pdev, pcie_dctl_reg, pcie_dctl);
-       }
+       if (pcie_dctl_reg)
+               if (pcie_set_readrq(ha->pdev, 2048))
+                       DEBUG2(printk("Couldn't write PCI Express read request\n"));

        /* Reset expansion ROM address decode enable */
        pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d);

---

-- 
AMD Saxony Limited Liability Company & Co. KG
Operating System Research Center
Wilschdorfer Landstr. 101, 01109 Dresden, Germany
Register Court Dresden: HRA 4896
General Partner authorized to represent:
AMD Saxony LLC (Wilmington, Delaware, US)
General Manager of AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy