From: "Robert Richter" <robert.richter@amd.com>
To: "Stephane Eranian" <eranian@hpl.hp.com>
Cc: "Andi Kleen" <andi@firstfloor.org>,
linux-kernel@vger.kernel.org,
"Robert Richter" <robert.richter@amd.com>
Subject: [patch 3/8] 2.6.22-rc3 perfmon2 : Minor changes
Date: Wed, 20 Jun 2007 20:41:31 +0200 [thread overview]
Message-ID: <20070620184131.GD5874@erda.amd.com> (raw)
In-Reply-To: 20070620182126.248753000@amd.com
[-- Attachment #1: perfmon2-fam10h-003.diff --]
[-- Type: text/plain, Size: 5098 bytes --]
Minor changes (whitespace, comments, ...)
Signed-off-by: Robert Richter <robert.richter@amd.com>
Index: linux-2.6.22-rc3/arch/x86_64/perfmon/perfmon_k8.c
===================================================================
--- linux-2.6.22-rc3.orig/arch/x86_64/perfmon/perfmon_k8.c
+++ linux-2.6.22-rc3/arch/x86_64/perfmon/perfmon_k8.c
@@ -1,5 +1,5 @@
/*
- * This file contains the PMU description for the Ahtlon64 and Opteron64
+ * This file contains the PMU description for the Athlon64 and Opteron64
* processors. It supports 32 and 64-bit modes.
*
* Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
@@ -32,23 +32,29 @@ static int force_nmi;
MODULE_PARM_DESC(force_nmi, "bool: force use of NMI for PMU interrupt");
module_param(force_nmi, bool, 0600);
-static struct pfm_arch_pmu_info pfm_k8_pmu_info={
+static struct pfm_arch_pmu_info pfm_k8_pmu_info = {
.pmc_addrs = {
- {{MSR_K7_EVNTSEL0, 0}, 0, PFM_REGT_EN},
- {{MSR_K7_EVNTSEL1, 0}, 1, PFM_REGT_EN},
- {{MSR_K7_EVNTSEL2, 0}, 2, PFM_REGT_EN},
- {{MSR_K7_EVNTSEL3, 0}, 3, PFM_REGT_EN},
+/* pmc0 */ {{MSR_K7_EVNTSEL0, 0}, 0, PFM_REGT_EN},
+/* pmc1 */ {{MSR_K7_EVNTSEL1, 0}, 1, PFM_REGT_EN},
+/* pmc2 */ {{MSR_K7_EVNTSEL2, 0}, 2, PFM_REGT_EN},
+/* pmc3 */ {{MSR_K7_EVNTSEL3, 0}, 3, PFM_REGT_EN},
},
.pmd_addrs = {
- {{MSR_K7_PERFCTR0, 0}, 0, PFM_REGT_CTR},
- {{MSR_K7_PERFCTR1, 0}, 0, PFM_REGT_CTR},
- {{MSR_K7_PERFCTR2, 0}, 0, PFM_REGT_CTR},
- {{MSR_K7_PERFCTR3, 0}, 0, PFM_REGT_CTR},
+/* pmd0 */ {{MSR_K7_PERFCTR0, 0}, 0, PFM_REGT_CTR},
+/* pmd1 */ {{MSR_K7_PERFCTR1, 0}, 0, PFM_REGT_CTR},
+/* pmd2 */ {{MSR_K7_PERFCTR2, 0}, 0, PFM_REGT_CTR},
+/* pmd3 */ {{MSR_K7_PERFCTR3, 0}, 0, PFM_REGT_CTR},
},
.pmu_style = PFM_X86_PMU_P6
};
/*
+ * force Local APIC interrupt on overflow
+ */
+#define PFM_K8_VAL (1ULL<<20)
+#define PFM_K8_NO64 (1ULL<<20)
+
+/*
* reserved bits must be zero
*
* - upper 32 bits are reserved
@@ -59,12 +65,6 @@ static struct pfm_arch_pmu_info pfm_k8_p
| (1ULL<<20) \
| (1ULL<<21))
-/*
- * force Local APIC interrupt on overflow
- */
-#define PFM_K8_VAL (1ULL<<20)
-#define PFM_K8_NO64 (1ULL<<20)
-
static struct pfm_reg_desc pfm_k8_pmc_desc[]={
/* pmc0 */ PMC_D(PFM_REG_I64, "PERFSEL0", PFM_K8_VAL, PFM_K8_RSVD, PFM_K8_NO64, MSR_K7_EVNTSEL0),
/* pmc1 */ PMC_D(PFM_REG_I64, "PERFSEL1", PFM_K8_VAL, PFM_K8_RSVD, PFM_K8_NO64, MSR_K7_EVNTSEL1),
@@ -73,11 +73,11 @@ static struct pfm_reg_desc pfm_k8_pmc_de
};
#define PFM_AMD_NUM_PMCS ARRAY_SIZE(pfm_k8_pmc_desc)
-static struct pfm_reg_desc pfm_k8_pmd_desc[]={
-/* pmd0 */ PMD_D(PFM_REG_C, "PERFCTR0", MSR_K7_PERFCTR0),
-/* pmd1 */ PMD_D(PFM_REG_C, "PERFCTR1", MSR_K7_PERFCTR1),
-/* pmd2 */ PMD_D(PFM_REG_C, "PERFCTR2", MSR_K7_PERFCTR2),
-/* pmd3 */ PMD_D(PFM_REG_C, "PERFCTR3", MSR_K7_PERFCTR3),
+static struct pfm_reg_desc pfm_k8_pmd_desc[] = {
+/* pmd0 */ PMD_D(PFM_REG_C, "PERFCTR0", MSR_K7_PERFCTR0),
+/* pmd1 */ PMD_D(PFM_REG_C, "PERFCTR1", MSR_K7_PERFCTR1),
+/* pmd2 */ PMD_D(PFM_REG_C, "PERFCTR2", MSR_K7_PERFCTR2),
+/* pmd3 */ PMD_D(PFM_REG_C, "PERFCTR3", MSR_K7_PERFCTR3),
};
#define PFM_AMD_NUM_PMDS ARRAY_SIZE(pfm_k8_pmd_desc)
Index: linux-2.6.22-rc3/include/asm-i386/perfmon.h
===================================================================
--- linux-2.6.22-rc3.orig/include/asm-i386/perfmon.h
+++ linux-2.6.22-rc3/include/asm-i386/perfmon.h
@@ -50,14 +50,14 @@
/*
* bitmask for reg_type
*/
-#define PFM_REGT_NA 0x00 /* not available */
-#define PFM_REGT_EN 0x01 /* has enable bit (cleared on ctxsw) */
-#define PFM_REGT_ESCR 0x02 /* P4: ESCR */
-#define PFM_REGT_CCCR 0x04 /* P4: CCCR */
-#define PFM_REGT_OTH 0x80 /* other type of register */
-#define PFM_REGT_PEBS 0x10 /* PEBS related */
-#define PFM_REGT_NOHT 0x20 /* unavailable with HT */
-#define PFM_REGT_CTR 0x40 /* counter */
+#define PFM_REGT_NA 0x0000 /* not available */
+#define PFM_REGT_EN 0x0001 /* has enable bit (cleared on ctxsw) */
+#define PFM_REGT_ESCR 0x0002 /* P4: ESCR */
+#define PFM_REGT_CCCR 0x0004 /* P4: CCCR */
+#define PFM_REGT_PEBS 0x0010 /* PEBS related */
+#define PFM_REGT_NOHT 0x0020 /* unavailable with HT */
+#define PFM_REGT_CTR 0x0040 /* counter */
+#define PFM_REGT_OTH 0x0080 /* other type of register */
/*
* This design and the partitioning of resources for SMT (hyper threads)
Index: linux-2.6.22-rc3/include/linux/perfmon_pmu.h
===================================================================
--- linux-2.6.22-rc3.orig/include/linux/perfmon_pmu.h
+++ linux-2.6.22-rc3/include/linux/perfmon_pmu.h
@@ -69,7 +69,7 @@ struct pfm_reg_desc {
#define PFM_REG_C64 0x04 /* PMD: 64-bit virtualization */
#define PFM_REG_RO 0x08 /* PMD: read-only (writes ignored) */
#define PFM_REG_V 0x10 /* PMD: virtual reg (provided by PMU description) */
-#define PFM_REG_NO64 0x100 /* PMC: supports REGFL_NOEMUL64 */
+#define PFM_REG_NO64 0x100 /* PMC: supports PFM_REGFL_NO_EMUL64 */
/*
* define some shortcuts for common types
--
AMD Saxony, Dresden, Germany
Operating System Research Center
email: robert.richter@amd.com
next prev parent reply other threads:[~2007-06-20 18:46 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20070620182126.248753000@amd.com>
2007-06-20 18:41 ` [patch 1/8] 2.6.22-rc3 perfmon2 : Barcelona CPU detection Robert Richter
2007-06-20 19:45 ` David Rientjes
2007-06-21 10:29 ` Robert Richter
2007-06-20 18:41 ` [patch 2/8] 2.6.22-rc3 perfmon2 : Debug messages added Robert Richter
2007-06-20 19:49 ` David Rientjes
2007-06-20 20:22 ` Stephane Eranian
2007-06-20 20:28 ` David Rientjes
2007-06-20 20:39 ` Stephane Eranian
2007-06-20 20:45 ` David Rientjes
2007-06-20 20:54 ` Stephane Eranian
2007-06-21 10:30 ` Robert Richter
2007-06-21 14:00 ` Robert Richter
2007-06-21 12:32 ` Andi Kleen
2007-06-20 18:41 ` Robert Richter [this message]
2007-06-20 18:41 ` [patch 4/8] 2.6.22-rc3 perfmon2 : Rearrangement of AMD64 MSR definitions, 2nd try Robert Richter
2007-06-20 18:41 ` [patch 5/8] 2.6.22-rc3 perfmon2 : Initial AMD64 PMU configuration Robert Richter
2007-06-20 18:41 ` [patch 6/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64 Robert Richter
2007-06-20 20:43 ` Stephane Eranian
2007-06-20 18:41 ` [patch 7/8] 2.6.22-rc3 perfmon2 : Renaming *_k8_* symbols to *_amd64_* Robert Richter
2007-06-20 19:43 ` David Rientjes
2007-06-21 14:00 ` Robert Richter
2007-06-20 18:42 ` [patch 8/8] 2.6.22-rc3 perfmon2 : Renaming of module perfmon_k8 to perfmon_amd64 Robert Richter
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