From: "Robert Richter" <robert.richter@amd.com>
To: "Stephane Eranian" <eranian@hpl.hp.com>,
"Andi Kleen" <andi@firstfloor.org>,
"David Rientjes" <rientjes@google.com>
Cc: linux-kernel@vger.kernel.org, "Robert Richter" <robert.richter@amd.com>
Subject: [patch 4/8] 2.6.22-rc3 perfmon2 : Rearrangement of AMD64 MSR definitions, 2nd try
Date: Wed, 20 Jun 2007 20:41:37 +0200 [thread overview]
Message-ID: <20070620184137.GE5874@erda.amd.com> (raw)
In-Reply-To: 20070620182126.248753000@amd.com
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David,
hex values are now lowercase, thanks. This also affects patch #6.
Andi,
since this is not a Perfmon specific patch, could you apply it?
Thanks,
-Robert
---------------
This patch rearranges AMD64 MSR definitions.
2nd try:
- hex values made lowercase
Signed-off-by: Robert Richter <robert.richter@amd.com>
Index: linux-2.6.22-rc3/include/asm-i386/msr-index.h
===================================================================
--- linux-2.6.22-rc3.orig/include/asm-i386/msr-index.h
+++ linux-2.6.22-rc3/include/asm-i386/msr-index.h
@@ -75,6 +75,18 @@
/* K7/K8 MSRs. Not complete. See the architecture manual for a more
complete list. */
+
+/* K8 MSRs */
+#define MSR_K8_TOP_MEM1 0xc001001a
+#define MSR_K8_TOP_MEM2 0xc001001d
+#define MSR_K8_SYSCFG 0xc0010010
+#define MSR_K8_HWCR 0xc0010015
+#define MSR_K8_ENABLE_C1E 0xc0010055
+#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
+#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
+#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
+
+/* K7 MSRs */
#define MSR_K7_EVNTSEL0 0xc0010000
#define MSR_K7_PERFCTR0 0xc0010004
#define MSR_K7_EVNTSEL1 0xc0010001
@@ -83,20 +95,10 @@
#define MSR_K7_PERFCTR2 0xc0010006
#define MSR_K7_EVNTSEL3 0xc0010003
#define MSR_K7_PERFCTR3 0xc0010007
-#define MSR_K8_TOP_MEM1 0xc001001a
#define MSR_K7_CLK_CTL 0xc001001b
-#define MSR_K8_TOP_MEM2 0xc001001d
-#define MSR_K8_SYSCFG 0xc0010010
-
-#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
-#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
-#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
-
#define MSR_K7_HWCR 0xc0010015
-#define MSR_K8_HWCR 0xc0010015
#define MSR_K7_FID_VID_CTL 0xc0010041
#define MSR_K7_FID_VID_STATUS 0xc0010042
-#define MSR_K8_ENABLE_C1E 0xc0010055
/* K6 MSRs */
#define MSR_K6_EFER 0xc0000080
--
AMD Saxony, Dresden, Germany
Operating System Research Center
email: robert.richter@amd.com
next prev parent reply other threads:[~2007-06-20 18:47 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20070620182126.248753000@amd.com>
2007-06-20 18:41 ` [patch 1/8] 2.6.22-rc3 perfmon2 : Barcelona CPU detection Robert Richter
2007-06-20 19:45 ` David Rientjes
2007-06-21 10:29 ` Robert Richter
2007-06-20 18:41 ` [patch 2/8] 2.6.22-rc3 perfmon2 : Debug messages added Robert Richter
2007-06-20 19:49 ` David Rientjes
2007-06-20 20:22 ` Stephane Eranian
2007-06-20 20:28 ` David Rientjes
2007-06-20 20:39 ` Stephane Eranian
2007-06-20 20:45 ` David Rientjes
2007-06-20 20:54 ` Stephane Eranian
2007-06-21 10:30 ` Robert Richter
2007-06-21 14:00 ` Robert Richter
2007-06-21 12:32 ` Andi Kleen
2007-06-20 18:41 ` [patch 3/8] 2.6.22-rc3 perfmon2 : Minor changes Robert Richter
2007-06-20 18:41 ` Robert Richter [this message]
2007-06-20 18:41 ` [patch 5/8] 2.6.22-rc3 perfmon2 : Initial AMD64 PMU configuration Robert Richter
2007-06-20 18:41 ` [patch 6/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64 Robert Richter
2007-06-20 20:43 ` Stephane Eranian
2007-06-20 18:41 ` [patch 7/8] 2.6.22-rc3 perfmon2 : Renaming *_k8_* symbols to *_amd64_* Robert Richter
2007-06-20 19:43 ` David Rientjes
2007-06-21 14:00 ` Robert Richter
2007-06-20 18:42 ` [patch 8/8] 2.6.22-rc3 perfmon2 : Renaming of module perfmon_k8 to perfmon_amd64 Robert Richter
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