From: Andi Kleen <andi@firstfloor.org>
To: Christoph Lameter <clameter@sgi.com>
Cc: Andi Kleen <andi@firstfloor.org>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/7] Simple Performance Counters: x86_64 support
Date: Wed, 1 Aug 2007 20:40:26 +0200 [thread overview]
Message-ID: <20070801184026.GC20713@one.firstfloor.org> (raw)
In-Reply-To: <Pine.LNX.4.64.0708011127490.22867@schroedinger.engr.sgi.com>
> It is certainly interesting to compare alternative ways of handling the
> instruction streams by various processors or models of processors.
Well you have to do a lot more work then to handle instable TSCs then.
In particular the frequencies can be different between CPUs, they
change (which you can catch with cpufreq notifiers) and during the
cpufreq change period they're instable (as in you can't tell for
some time which frequency they're currently running at and they
might be running immediate frequencies)
The current cycles_2_ns() users avoid this problem by not
using the TSC in this case, but that might not be an option
for you (cpufreq is becoming more and more ubiquitous)
Good luck.
-Andi
next prev parent reply other threads:[~2007-08-01 18:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-07-31 23:25 [PATCH 2/7] Simple Performance Counters: x86_64 support Christoph Lameter
2007-08-01 10:53 ` Andi Kleen
2007-08-01 17:52 ` Christoph Lameter
2007-08-01 18:26 ` Andi Kleen
2007-08-01 18:29 ` Christoph Lameter
2007-08-01 18:40 ` Andi Kleen [this message]
2007-08-01 18:45 ` Christoph Lameter
2007-08-01 18:57 ` Andi Kleen
2007-08-01 18:58 ` Christoph Lameter
2007-08-01 19:15 ` Andi Kleen
2007-08-17 16:10 ` Mathieu Desnoyers
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