Re: LFENCE instruction (was: [rfc][patch 3/3] x86: optimise barriers)

Mikulas Patocka
2007-10-16T23:05:29Z

> > I see, AMD says that WC memory loads can be out-of-order.
> >
> > There is very little usability to it --- framebuffer and AGP aperture is
> > the only piece of memory that is WC and no kernel structures are placed
> > there, so it is possible to remove that lfence.
>
> No. In Linux kernel, rmb() means that all previous loads, including to
> any IO regions, will be executed before any subsequent load.

You already must not place any data structures into WC memory --- for
example, spinlocks wouldn't work there. wmb() also won't work on WC
memory, because it assumes that writes are ordered.

> How can you possibly get rid of lfence from there just because you may
> happen to *know* that it isn't used (btw. the IO serialisation isn't for
> kernel data structures, it is for actual IO operations, generally).

IO regions are in uncached memory, and x86 already serializes it fine. It
flushes any write buffers on access to uncached memory.

(BTW. what is the general portable rule for serializing writel() and
readl()? On x86 they are serialized in hardware, but what on other archs?)

> Doing that would lead to an unmaintainable mess. If drivers don't need rmb,
> then they don't call it.

If wmb() doesn't currently work on write-combining memory, why should
rmb() work there?

The purpose of rmb() is to enforce ordering on architectures that don't
force it in hardware --- that is not the case of x86.

Mikulas