From: Robert Richter <robert.richter@amd.com>
To: stephane eranian <eranian@googlemail.com>
Cc: linux-kernel@vger.kernel.org, akpm@linux-foundation.org, ak@suse.de
Subject: Re: [PATCH 2/3] perfmon x86 infrastructure definitions
Date: Fri, 7 Mar 2008 12:42:50 +0100 [thread overview]
Message-ID: <20080307114249.GA12930@erda.amd.com> (raw)
In-Reply-To: <7c86c4470803062225y4727a19ic321314b292dd874@mail.gmail.com>
On 06.03.08 22:25:26, stephane eranian wrote:
> adds AMD Northbridge config MSR definition
>
> Signed-off-by: Stephane Eranian <eranian@gmail.com>
> Signed-off-by: Robert Richter <robert.richter@amd.com>
> --- a/include/asm-x86/msr-index.h
> +++ b/include/asm-x86/msr-index.h
> @@ -83,6 +83,7 @@
> /* AMD64 MSRs. Not complete. See the architecture manual for a more
> complete list. */
>
> +#define MSR_AMD64_NB_CFG 0xc001001f
This will probably not be needed after mm config works fine (patches
from Yinghai Lu). Since the usage of CF8 extended configuration cycles
is not recommended, the current code to enable IBS interrupts can be
seen as temporary. I will rework the IBS code so that it uses mm
config.
-Robert
--
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com
next prev parent reply other threads:[~2008-03-07 11:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-03-07 6:25 [PATCH 2/3] perfmon x86 infrastructure definitions stephane eranian
2008-03-07 11:42 ` Robert Richter [this message]
2008-03-07 21:01 ` stephane eranian
2008-03-10 8:55 ` Robert Richter
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