* [PATCH 2/3] perfmon x86 infrastructure definitions
@ 2008-03-07 6:25 stephane eranian
2008-03-07 11:42 ` Robert Richter
0 siblings, 1 reply; 4+ messages in thread
From: stephane eranian @ 2008-03-07 6:25 UTC (permalink / raw)
To: linux-kernel; +Cc: akpm, ak, Robert Richter
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adds AMD Northbridge config MSR definition
Signed-off-by: Stephane Eranian <eranian@gmail.com>
Signed-off-by: Robert Richter <robert.richter@amd.com>
[-- Attachment #2: x86-add-nb-cfg-msr.diff --]
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--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -83,6 +83,7 @@
/* AMD64 MSRs. Not complete. See the architecture manual for a more
complete list. */
+#define MSR_AMD64_NB_CFG 0xc001001f
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH 2/3] perfmon x86 infrastructure definitions
2008-03-07 6:25 [PATCH 2/3] perfmon x86 infrastructure definitions stephane eranian
@ 2008-03-07 11:42 ` Robert Richter
2008-03-07 21:01 ` stephane eranian
0 siblings, 1 reply; 4+ messages in thread
From: Robert Richter @ 2008-03-07 11:42 UTC (permalink / raw)
To: stephane eranian; +Cc: linux-kernel, akpm, ak
On 06.03.08 22:25:26, stephane eranian wrote:
> adds AMD Northbridge config MSR definition
>
> Signed-off-by: Stephane Eranian <eranian@gmail.com>
> Signed-off-by: Robert Richter <robert.richter@amd.com>
> --- a/include/asm-x86/msr-index.h
> +++ b/include/asm-x86/msr-index.h
> @@ -83,6 +83,7 @@
> /* AMD64 MSRs. Not complete. See the architecture manual for a more
> complete list. */
>
> +#define MSR_AMD64_NB_CFG 0xc001001f
This will probably not be needed after mm config works fine (patches
from Yinghai Lu). Since the usage of CF8 extended configuration cycles
is not recommended, the current code to enable IBS interrupts can be
seen as temporary. I will rework the IBS code so that it uses mm
config.
-Robert
--
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/3] perfmon x86 infrastructure definitions
2008-03-07 11:42 ` Robert Richter
@ 2008-03-07 21:01 ` stephane eranian
2008-03-10 8:55 ` Robert Richter
0 siblings, 1 reply; 4+ messages in thread
From: stephane eranian @ 2008-03-07 21:01 UTC (permalink / raw)
To: Robert Richter; +Cc: linux-kernel, akpm, ak
Robert,
On Fri, Mar 7, 2008 at 3:42 AM, Robert Richter <robert.richter@amd.com> wrote:
>
> On 06.03.08 22:25:26, stephane eranian wrote:
> > adds AMD Northbridge config MSR definition
> >
> > Signed-off-by: Stephane Eranian <eranian@gmail.com>
> > Signed-off-by: Robert Richter <robert.richter@amd.com>
>
> > --- a/include/asm-x86/msr-index.h
> > +++ b/include/asm-x86/msr-index.h
> > @@ -83,6 +83,7 @@
> > /* AMD64 MSRs. Not complete. See the architecture manual for a more
> > complete list. */
> >
> > +#define MSR_AMD64_NB_CFG 0xc001001f
>
> This will probably not be needed after mm config works fine (patches
> from Yinghai Lu). Since the usage of CF8 extended configuration cycles
> is not recommended, the current code to enable IBS interrupts can be
> seen as temporary. I will rework the IBS code so that it uses mm
> config.
>
Ok, but I want to push what we have now. We can change this later.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2008-03-07 6:25 [PATCH 2/3] perfmon x86 infrastructure definitions stephane eranian
2008-03-07 11:42 ` Robert Richter
2008-03-07 21:01 ` stephane eranian
2008-03-10 8:55 ` Robert Richter
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