Re: [BISECTED] Lots of "rescheduling IPIs" in powertop

[Andreas Herrmann <andreas.herrmann3@amd.com>]

On Wed, May 14, 2008 at 01:42:54PM +0200, Andi Kleen wrote:
> Andreas Herrmann <andreas.herrmann3@amd.com> writes:
> >
> > It depends on the CPU. For AMD CPUs that support MWAIT this is wrong.
> > Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings then
>                                 ^ not

Not sure what you meant by your comment.
Maybe you should re-read the paragraph.

It's as simple as that:
If OS executes Halt the core enters C1.
The core exits C1 if an interrupt is received.

> > It might be best to switch off the mwait flag for these AMD CPU
> > families like it was introduced with commit
> > f039b754714a422959027cb18bb33760eb8153f0 (x86: Don't use MWAIT on AMD
> > Family 10)
> 
> Then you have to special case everything again. We still need to 
> work out if the P4 is even correct here or not, but if it's not
> i would rather quirk the cpuid reporting on it.

I just want to ensure that for AMD family 0x10 and 0x11 halt and not
mwait is executed when the core is idle.


Andreas