From: "Yang, Sheng" <sheng.yang@intel.com>
To: linux-pci@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] PCI: Add Bridge Configuration Retry bit in PCIE Control
Date: Thu, 10 Jul 2008 14:41:25 +0800 [thread overview]
Message-ID: <200807101441.25611.sheng.yang@intel.com> (raw)
In-Reply-To: <200807101145.43839.sheng.yang@intel.com>
[-- Attachment #1: Type: text/plain, Size: 1812 bytes --]
Updated patch with FLR capability indicated bit...
From a6478de8d190a0343580023aa93c968e6b369c51 Mon Sep 17 00:00:00 2001
From: Sheng Yang <sheng.yang@intel.com>
Date: Thu, 10 Jul 2008 14:39:13 +0800
Subject: [PATCH] PCI: Add Function Level Reset related bits
The bit 28 in PCI-E Capability Register indicated Function Level Reset
capability.
The bit 15 in PCI-E Control Register is Bridge Configuration Retry
Reset and
Initiate Function Level Reset bit.
Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
include/linux/pci_regs.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223..b656d22 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -375,6 +375,7 @@
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value
*/
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale
*/
+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting
En. */
#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting
Enable */
@@ -387,6 +388,7 @@
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable
*/
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration
Retry / FLR */
#define PCI_EXP_DEVSTA 10 /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
--
1.5.6
[-- Attachment #2: 0001-PCI-Add-Function-Level-Reset-related-bits.patch --]
[-- Type: text/x-diff, Size: 1745 bytes --]
From a6478de8d190a0343580023aa93c968e6b369c51 Mon Sep 17 00:00:00 2001
From: Sheng Yang <sheng.yang@intel.com>
Date: Thu, 10 Jul 2008 14:39:13 +0800
Subject: [PATCH] PCI: Add Function Level Reset related bits
The bit 28 in PCI-E Capability Register indicated Function Level Reset
capability.
The bit 15 in PCI-E Control Register is Bridge Configuration Retry Reset and
Initiate Function Level Reset bit.
Signed-off-by: Sheng Yang <sheng.yang@intel.com>
---
include/linux/pci_regs.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223..b656d22 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -375,6 +375,7 @@
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
#define PCI_EXP_DEVCTL 8 /* Device Control */
#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
@@ -387,6 +388,7 @@
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
#define PCI_EXP_DEVSTA 10 /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
--
1.5.6
prev parent reply other threads:[~2008-07-10 6:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-07-10 3:45 [PATCH] PCI: Add Bridge Configuration Retry bit in PCIE Control Yang, Sheng
2008-07-10 6:41 ` Yang, Sheng [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=200807101441.25611.sheng.yang@intel.com \
--to=sheng.yang@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox