Re: [PATCH]: PCI: GART iommu alignment fixes [v2]

[Joerg Roedel <joro@8bytes.org>]

On Wed, Jul 23, 2008 at 07:47:03PM -0400, Prarit Bhargava wrote:
> 
> >>Interesting. Have you experienced any problems because of that
> >>misbehavior in the GART code? AMD IOMMU currently also violates this
> >>requirement. I will send a patch to fix that there too.
> >>    
> >
> >  
> 
> Joerg,  yes I can see misbehavior caused by this code.  O/w I wouldn't 
> be spending my time fixing it :) :)
> 
> See below ....
> 
> >IIRC, only PARISC and POWER IOMMUs follow the above rule. So I also
> >wondered what problem he hit.
> >  
> 
> I wonder if IBM's Calgary IOMMU needs this fix? ... I've added Ed 
> Pollard to find out.
> 
> On big memory footprint (16G or above) systems it is possible that the 
> e820 map reserves most of the lower 4G of memory for system use*.  So 
> it's possible that the 4G region is almost completely reserved at boot 
> time and so the kernel starts using the IOMMU for DMA (see 
> dma_alloc_coherent()).  The addresses returned are not properly aligned, 
> and this causes serious problems for some drivers that require a 
> physical aligned address for the device.

Do you have a list of driver which require this? I would like to
reproduce this issue. Does it also happen when you start the kernel with
iommu=force (GART should then be used for all DMA remapping) too?

Joerg