Re: [PATCH] x86 (64): make calibrate_APIC_clock() SMI-safe (take 3)

[Cyrill Gorcunov <gorcunov@gmail.com>]

[Martin Wilck - Fri, Jul 25, 2008 at 04:01:08PM +0200]
> Cyrill Gorcunov wrote:
>
>> Martin, if I understood you right - this means your patch is not
>> needed? 
>
> The patch would still be needed. Just the reported failure of my  
> simplified patch on the old kernel would not have occurred in the  
> current kernel. IOW, the patch is fine for the current kernel, but not  
> for the old one.
>
>> Actually on 64bit mode APIC_DIVISOR is a bit hidden in
>> __setup_APIC_LVTT - you may see it as APIC_TDR_DIV_16 while setting
>> up divisor register. I was proposing patch for that but it leaded
>> to potetntial overflow (thanks Ingo for catching) so we leave it as
>> is. Maybe I miss something?
>
> The problem was not that the divisor 16 was used for the counter speed  
> (APIC_TDR_DIV_16), but that the old code set the counter start value to  
> (250000000/16) rather than just 250000000. That means the counter will  
> underflow earlier.
>
> I am attaching a "take 3" patch which minimizes the risk of an underflow  
> by using the maximum possible initial value for the APIC timer.
>
> Martin
>

Martin, it seems you forgot to attach the patch :) (since it was
continious tense I thought I would see patch in minute but...
it was not eventually apeeared :)

		- Cyrill -