Re: [PATCH 01/01] x86: L3 cache index disable for 2.6.26

[Pavel Machek <pavel@suse.cz>]

Hi!

> New versions of AMD processors have support to disable parts
> of their L3 caches if too many MCEs are generated by the
> L3 cache.  
> 
> This patch provides a /sysfs interface under the cache
> hierarchy to display which caches indices are disabled
> (if any) and to monitoring applications to disable a
> cache index.
...

> +static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
> +{
> +	struct pci_dev *dev;
> +	if (this_leaf->can_disable) {
> +		int i;
> +		ssize_t ret = 0;
> +		int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
> +		dev = k8_northbridges[node];
> +
> +		for (i = 0; i < 2; i++) {
> +			unsigned int reg;
> +			pci_read_config_dword(dev, 0x1BC + i * 4, &reg);
> +			ret += sprintf(buf, "%sEntry: %d\n", buf, i);
> +			ret += sprintf(buf, "%sReads:  %s\tNew Entries: %s\n",  
> +				buf,
> +				reg & 0x80000000 ? "Disabled" : "Allowed",
> +				reg & 0x40000000 ? "Disabled" : "Allowed");
> +			ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n", buf,
> +				(reg & 0x30000) >> 16, reg & 0xfff);
> +
> +		}
> +		return ret;
> +	}
> +	return sprintf(buf, "Feature not enabled\n");
> +}

I think there's one-value-per-file rule in sysfs...

I guess it is better to return -EOPNOTSUP (or something) instead of
english text explaining that...

No, really, what you created is impossible to parse -- /proc like
nightmare.

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html