[PATCH 2/4] Add cpufreq driver for the IBM PowerPC 750GX

Kevin Diggs
2008-08-25T10:54:58Z

This adds the actual cpufreq driver for the 750GX. It supports all integer
ratios that are valid for the processor model and bus frequency.

It has two modes of operation. Normal mode uses all valid frequencies. In
minmaxmode, only the minimum and maximum are used. This provides the ability
for very low latency frequency switches.

There is also a sysfs attribute to have it switch off the unused PLL for
additional power savings.

This does NOT support SMP.

My name is Kevin Diggs and I approve this patch.

Signed-off-by: Kevin Diggs <kevdig@hypersurf.com>
Index: Documentation/DocBook/cf750gx.tmpl
===================================================================
--- /dev/null 2004-08-10 18:55:00.000000000 -0700
+++ Documentation/DocBook/cf750gx.tmpl 2008-08-20 10:00:14.000000000 -0700
@@ -0,0 +1,441 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
+ "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
+
+<book id="ppc750gx-cpufreq-guide">
+ <bookinfo>
+ PowerPC 750GX (and FX?) cpufreq driver guide
+
+ <authorgroup>
+ <author>
+ <firstname>Kevin</firstname>
+ <surname>Diggs</surname>
+ </author>
+ </authorgroup>
+
+ <revhistory>
+ <revision>
+ <revnumber>1.0&nbsp;</revnumber>
+ <date>August 12, 2008</date>
+ <revremark>Initial revision posted to linuxppc-dev</revremark>
+ </revision>
+ </revhistory>
+
+ <copyright>
+ <year>2008</year>
+ <holder>Kevin Diggs</holder>
+ </copyright>
+
+ <legalnotice>
+
+ This documentation is free software; you can redistribute
+ it and/or modify it under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later
+ version.
+
+
+
+ This program is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU General Public License for more details.
+
+
+
+ You should have received a copy of the GNU General Public
+ License along with this program; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ MA 02111-1307 USA
+
+
+
+ For more details see the file COPYING in the source
+ distribution of Linux.
+
+ </legalnotice>
+
+ <releaseinfo>
+ This is the first release of this document coincident with submission of the
+ driver for inclusion in the kernel.
+ </releaseinfo>
+
+ </bookinfo>
+
+ <toc></toc>
+
+ <chapter id="introduction">
+ Introduction
+
+ This guide documents the cpufreq driver for the IBM PowerPC 750GX processor.
+ It "should" also work with the 750FX but has not been tested.
+
+
+ The driver is split into two main parts. The first provides the low level
+ interface to the PLL configuration register (HID1 - SPR 1009). It is called
+ pll_if. The second is the actual cpufreq driver, called cf750gx. The pll_if
+ component handles the details of dealing with the PLL like PLL lock delay
+ requirements and preventing illegal operations. The cf750gx driver provides
+ the interface to the cpufreq subsystem. Under control of the specified
+ governor it will generate the required commands to switch the processor
+ frequency as requested and send them to pll_if to carry them out.
+
+ </chapter>
+
+ <chapter id="MajorComponents">
+ Major Components
+
+
+ The IBM 750GX (and FX) processor has a pair of PLLs that can be programmed to
+ operate at a number of different frequencies. The frequencies are specified
+ as ratios to the system bus and range from 2 to 20. From 2 to 10 it also
+ supports half ratios (i.e. 2.5, 3.5) though they are not supported in the
+ cpufreq driver due to a limitation of not being able to switch from one half
+ ratio directly to another. It takes 100 usec for a PLL to relock to a
+ new frequency before it can be used [750GX_ds2-17-05.pdf, Table 3-7,
+ page 18]. It takes 3 bus clocks for the cpu to switch from one PLL to
+ another [750GX_ds2-17-05.pdf, paragraph 3, page 44].
+
+
+
+ The cpufreq driver consists of two main parts:
+
+
+
+
+
+ cf750gx - the cpufreq driver module
+
+
+
+
+
+ pll_if - a low level interface that encapsulates the details of dealing
+ with the PLL register
+
+
+
+
+ <sect1 id="cf750gx">
+ cf750gx - The CPUFreq 750GX driver
+
+
+ cf750gx provides the standard entry points required of a cpufreq driver. They
+ are:
+
+
+
+
+ cf750gx_verify - verify
+
+
+
+
+
+ cf750gx_target - target
+
+
+
+
+
+ cf750gx_cpu_init - cpu init
+
+
+
+
+
+ cf750gx_cpu_exit - cpu exit
+
+
+
+
+ These routines perform functions as required by the cpufreq subsystem.
+
+
+
+ The driver functions in one of 2 modes: normal and minmax. In normal mode
+ it switches between the available frequencies as requested by the current
+ cpufreq subsystem governor. In minmax mode, it switches between the minimum
+ and maximum frequencies only.
+
+
+ <sect2 id="cf750gxModesNormal"> Normal Mode
+
+ In normal mode the driver switches between all valid frequencies under
+ control of the selected governor. The list of valid frequencies is
+ determined at startup based on the cpu model (FX or GX) and the determined
+ bus frequency. The cpu model determines the minimum and maximum core
+ frequencies, though these can be overriden at start up via module
+ parameters. See Module Parameters. The bus frequency is obtained from
+ pll_if.
+
+ </sect2>
+
+ <sect2 id="cf750gxModesMinMax"> MinMax Mode
+
+ In minmax mode the driver switches between the minimum and maximum core
+ frequencies only. This provides the capability for very low latency
+ frequency switches. See Module Parameters and sysfs Attributes.
+
+ </sect2>
+
+ <sect2 id="cf750gxModuleParameters"> Module Parameters
+
+ cf750gx has 3 module parameters:
+
+
+
+
+
+ override_max_core
+
+
+
+
+ override_min_core
+
+
+
+
+ minmaxmode
+
+
+
+
+ <sect3 id="cf750gxParamOverrideMaxCore"> override_max_core
+
+ Normally the maximum frequency the cpu can be clocked is defined by the
+ cpu model. For the FX it is 800 MHz and 1,000 MHz for the GX. This
+ parameter allows you to override this maximum. It is specified in KHz.
+
+ </sect3>
+
+ <sect3 id="cf750gxParamOverrideMinCore"> override_min_core
+
+ Likewise for cpu minimum frequency.
+
+
+ <note>
+
+ The 750GX on my PowerForce 750GX cpu upgrade seems stable at 250 MHz.
+ The spec says the minimum for the GX is 500 MHz.
+
+ </note>
+ </sect3>
+
+ <sect3 id="cf750gxParamMinMaxMode"> minmaxmode
+
+ This boolean parameter allows one to enable minmax mode on startup.
+
+ </sect3>
+ </sect2>
+
+ <sect2 id="cf750gxsysfsAttributes"> sysfs Attributes
+
+ cf750gx has 2 sysfs attributes that can be used to modify its operation.
+ They are:
+
+
+
+
+ idle_pll_off
+
+
+
+
+
+ min_max_mode
+
+
+
+
+ Both are booleans.
+
+
+ <sect3 id="IdlePllOffAttr"> idle_pll_off
+
+ This boolean tells the driver to switch the idle PLL (the one NOT
+ currently used to drive the cpu core clock) off. Turning the unused PLL
+ off results in a modest power savings [750GX_ds2-17-05.pdf,
+ section 5.2.1, page 44].
+
+ </sect3>
+
+ <sect3 id="MinMaxModeAttr"> min_max_mode
+
+ This attribute controls the same feature as the similarly named module
+ parameter.
+
+
+ <note>
+
+ In order to get this to work with the conservative governor, the
+ "freq_step" attribute must be set to a value that will pick the max
+ frequency from the 2 element frequency table. A good value is 80 (which
+ says to jump in frequency by 80% of the maximum on each change).
+
+ </note>
+ </sect3>
+ </sect2>
+ </sect1>
+
+ <sect1 id="pll_if">
+ pll_if - The Low Level PLL Interface Module
+
+ pll_if provides the choice of two interfaces to control the PLL register.
+ One is via a sysfs attribute. The other is through an exported, public
+ routine. At least one interface must be selected during kernel
+ configuration.
+
+
+ <sect2 id="sysfsInterface"> sysfs Interface - ppc750gxpll
+
+ This interface provides a sysfs attribute that can be written to to
+ directly control the PLL configuration register. The upper 8 or so bits of
+ the PLL configuration register are read only. This interface takes
+ advantage of this by using these bits to define which of the writeable
+ bits contain valid data. The header file
+ <filename class="headerfile">include/asm-powerpc/pll_if.h</filename>
+ defines the following macros:
+
+
+
+
+ PLL0_DO_CFG - PLL 0 config (ratio) valid
+
+
+
+
+
+ PLL0_DO_RNG - PLL 0 range valid
+
+
+
+
+
+ PLL1_DO_CFG - PLL 1 config (ratio) valid
+
+
+
+
+
+ PLL1_DO_RNG - PLL 1 range valid
+
+
+
+
+
+ PLL_DO_SEL - PLL selection bit valid
+
+
+
+
+ See the PERL script pll.pl for an example of using the sysfs attribute.
+
+ </sect2>
+
+ <sect2 id="PublicAPI"> Exported, Public Functions Interface
+
+ This interface provides a public API that other code can use. The list of
+ functions is:
+
+
+
+
+ pllif_pack_state
+
+
+
+
+
+ pllif_get_latency
+
+
+
+
+
+ pllif_modify_PLL
+
+
+
+
+
+ pllif_get_bus_clock
+
+
+
+
+
+ pllif_cfg_to_freq
+
+
+
+
+
+ pllif_register_pll_switch_cb
+
+
+
+
+
+ pllif_unregister_pll_switch_cb
+
+
+
+
+
+ pllif_register_pll_lock_cb
+
+
+
+
+
+ pllif_unregister_pll_lock_cb
+
+
+
+
+
+ The embedded documentation from
+ <filename class="headerfile">include/asm-powerpc/pll_if.h</filename>
+ and
+ <filename class="headerfile">arch/powerpc/kernel/cpu/pll_if.c</filename>
+ is included in the appendix.
+
+
+ </sect2>
+
+ <sect2 id="pllifModuleParameters"> Module Parameters
+
+ pll_if has one tunable parameter. override_bus_clock allows you to specify
+ the bus frequency. This is useful if the code can not determine the value
+ or gets it wrong. It is in KHz.
+
+
+ <note>
+
+ This code was developed on a PowerMac 8600 with a PowerLogix 750GX
+ upgrade card in it. The method used in the code to get the bus frequency
+ is what worked on this system.
+
+ </note>
+ </sect2>
+ </sect1>
+ </chapter>
+
+ <chapter id="Misc"> Misc
+ <sect1 id="pll.pl"> pll.pl - A User Friendly pll_if sysfs utility
+
+ pll.pl is a PERL script that provides a user friendly interface to the
+ pll_if sysfs attribute, cf750gxpll. It provides options to query the
+ current PLL state, change the configuration of either PLL (when inactive),
+ and to switch the PLL in use. See the embedded documentation in pll.pl
+ for details.
+
+ </sect1>
+ </chapter>
+ <chapter id="Appendix"> Appendix
+!Finclude/asm-powerpc/pll_if.h pllifGetLatency pllifPackState
+!Earch/powerpc/kernel/cpu/pll_if.c
+ </chapter>
+</book>
Index: Documentation/DocBook/Makefile
===================================================================
--- Documentation/DocBook/Makefile.orig 2008-08-13 02:18:51.000000000 -0700
+++ Documentation/DocBook/Makefile 2008-08-14 02:47:33.000000000 -0700
@@ -12,7 +12,7 @@ DOCBOOKS := wanbook.xml z8530book.xml mc
kernel-api.xml filesystems.xml lsm.xml usb.xml kgdb.xml \
gadget.xml libata.xml mtdnand.xml librs.xml rapidio.xml \
genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \
- mac80211.xml debugobjects.xml
+ mac80211.xml debugobjects.xml cf750gx.xml

###
# The build process is as follows (targets):
Index: arch/powerpc/kernel/cpu/cpufreq/Kconfig
===================================================================
--- /dev/null 2004-08-10 18:55:00.000000000 -0700
+++ arch/powerpc/kernel/cpu/cpufreq/Kconfig 2008-08-19 00:24:15.000000000 -0700
@@ -0,0 +1,33 @@
+#
+# CPU Frequency scaling
+#
+
+menu "CPU Frequency scaling"
+
+source "drivers/cpufreq/Kconfig"
+
+if CPU_FREQ
+
+comment "CPUFreq processor drivers"
+
+config CPU_FREQ_PPC_750GX_DUAL_PLL
+ tristate "PowerPC 750 FX/GX Dual PLL driver"
+ depends on !SMP
+ select PPC_750GX_DUAL_PLL_IF
+ select CPU_FREQ_TABLE
+ help
+ This driver adds a CPUFreq driver which utilizes the dual
+ PLLs found in the IBM 750 FX & GX cpus. This will automatically
+ select the pll_if module. It does NOT support SMP.
+
+ To compile this driver as a module, choose M here: the
+ module will be called cf750gx.
+
+ For details, take a look at <file:Documentation/cpu-freq/> and also
+ see the cf750gx DocBook.
+
+ If in doubt, say N.
+
+endif # CPU_FREQ
+
+endmenu
Index: arch/powerpc/kernel/cpu/cpufreq/Makefile
===================================================================
--- /dev/null 2004-08-10 18:55:00.000000000 -0700
+++ arch/powerpc/kernel/cpu/cpufreq/Makefile 2008-08-14 02:44:30.000000000 -0700
@@ -0,0 +1 @@
+obj-$(CONFIG_CPU_FREQ_PPC_750GX_DUAL_PLL) += cf750gx.o
Index: arch/powerpc/kernel/cpu/cpufreq/cf750gx.c
===================================================================
--- /dev/null 2004-08-10 18:55:00.000000000 -0700
+++ arch/powerpc/kernel/cpu/cpufreq/cf750gx.c 2008-08-22 15:54:48.000000000 -0700
@@ -0,0 +1,736 @@
+/*
+ * cf750gx.c - cpufreq driver for the dual PLLs in the 750gx
+ *
+ * Copyright (C) 2008 kevin Diggs
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/cpufreq.h>
+#include <linux/compiler.h>
+#include <linux/dmi.h>
+#include <linux/delay.h>
+#include "linux/completion.h"
+
+#include <asm/processor.h>
+#include "asm/pll.h"
+#include "asm/pll_if.h"
+#include "asm/time.h"
+
+#define cf750gxmChangingPll (0x80000000)
+#define cf750gxmChangingPllBit (31)
+#define cf750gxmTurningIdlePllOff (0x40000000)
+#define cf750gxmTurningIdlePllOffBit (30)
+
+struct pll_750fgx_t {
+ unsigned short min_ratio; /* min bus ratio */
+ unsigned short max_ratio; /* max bus ratio */
+ unsigned int min_core; /* min core frequency per spec (KHz) */
+ unsigned int max_core; /* max core frequency per spec (KHz) */
+};
+
+#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
+ "ppc-750gx-cpufreq", msg)
+
+MODULE_AUTHOR("Kevin Diggs");
+MODULE_DESCRIPTION("750GX Dual PLL cpufreq driver");
+MODULE_LICENSE("GPL");
+
+struct cf750gx_t_call_data {
+ struct cpufreq_freqs freqs;
+ unsigned long current_pll;
+ int idle_pll_off;
+};
+
+static const struct pll_750fgx_t __initdata pll_750fx = {
+ .min_ratio = 2,
+ .max_ratio = 20,
+ .min_core = 400000,
+ .max_core = 800000,
+};
+
+static const struct pll_750fgx_t __initdata pll_750gx = {
+ .min_ratio = 2,
+ .max_ratio = 20,
+ .min_core = 500000,
+ .max_core = 1000000,
+};
+
+static DECLARE_COMPLETION(cf750gx_v_exit_completion);
+
+static unsigned int override_min_core = 0;
+static unsigned int override_max_core = 0;
+static unsigned int minmaxmode = 0;
+
+static unsigned int cf750gx_v_min_core = 0;
+static unsigned int cf750gx_v_max_core = 0;
+static int cf750gx_v_idle_pll_off = 0;
+static int cf750gx_v_min_max_mode = 0;
+static unsigned long cf750gx_v_state_bits = 0;
+
+static struct cpufreq_frequency_table *cf750gx_v_f_table;
+static struct cpufreq_frequency_table *cf750gx_v_freq_table;
+static struct cpufreq_frequency_table *cf750gx_v_min_max_freq_table;
+
+static struct cf750gx_t_call_data cf750gx_v_switch_call_data;
+static struct cf750gx_t_call_data cf750gx_v_lock_call_data;
+static struct notifier_block cf750gx_v_pll_switch_nb;
+static struct notifier_block cf750gx_v_pll_lock_nb;
+
+static int cf750gx_pll_switch_cb(struct notifier_block *nb, unsigned long
+ action, void *data)
+{
+struct cf750gx_t_call_data *cd;
+unsigned int idle_pll;
+unsigned int pll_off_cmd;
+unsigned int new_pll;
+
+ cd = (struct cf750gx_t_call_data *)data;
+
+ dprintk("%s(): cd->idle_pll_off is %d, new PLL is 0x%x"
+ ", Switched to %d KHz\n", __func__, cd->idle_pll_off,
+ cd->current_pll, cd->freqs.new);
+
+ cpufreq_notify_transition(&cd->freqs, CPUFREQ_POSTCHANGE);
+
+ if (cd->idle_pll_off) {
+ /*
+ * Assemble call to turn idle PLL off. Use the value of
+ * current_pll in the call data thing.
+ */
+ idle_pll = get_next_PLL(cd->current_pll)^0x1;
+
+ pll_off_cmd = pllif_pack_state(0, 2);
+
+ /*
+ * Put in correct spot
+ */
+ if (idle_pll) {
+ /*
+ * Use PLL 1
+ */
+ new_pll = ((PLL1_DO_CFG|PLL1_DO_RNG)<<24);
+ } else {
+ /*
+ * Since active PLL is 1, switch off PLL 0
+ */
+ pll_off_cmd = pll_off_cmd<<(PLL0_CFG_SHIFT-
+ PLL1_CFG_SHIFT);
+
+ new_pll = (PLL0_DO_CFG|PLL0_DO_RNG)<<24;
+ }
+
+ new_pll = new_pll|pll_off_cmd;
+
+ set_bit(cf750gxmTurningIdlePllOffBit, &cf750gx_v_state_bits);
+
+ (void) pllif_modify_PLL(new_pll, 0);
+ } else {
+ clear_bit(cf750gxmChangingPllBit, &cf750gx_v_state_bits);
+
+ complete(&cf750gx_v_exit_completion);
+ }
+
+ return NOTIFY_OK;
+}
+
+static int cf750gx_pll_lock_cb(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+struct cf750gx_t_call_data *cd;
+
+ cd = (struct cf750gx_t_call_data *)data;
+
+ dprintk("%s(): cd->idle_pll_off is %d, new PLL is 0x%x"
+ ", Switched to %d KHz\n", __func__, cd->idle_pll_off,
+ cd->current_pll, cd->freqs.new);
+
+ if (cd->idle_pll_off) {
+ /*
+ * We want to turn off the inactive (idle) pll. Use the state
+ * bits global to figure out whether this call back is for the
+ * original, cpufreq ordered frequency change or our turning
+ * off of the idle PLL.
+ */
+ if (test_bit(cf750gxmTurningIdlePllOffBit,
+ &cf750gx_v_state_bits)) {
+ clear_bit(cf750gxmTurningIdlePllOffBit,
+ &cf750gx_v_state_bits);
+ clear_bit(cf750gxmChangingPllBit,
+ &cf750gx_v_state_bits);
+ complete(&cf750gx_v_exit_completion);
+ }
+ }
+
+ return NOTIFY_OK;
+}
+
+static inline const char *cf750gx_i_relation_str(unsigned int relation)
+{
+ switch (relation) {
+ case CPUFREQ_RELATION_L: return "CPUFREQ_RELATION_L";
+ case CPUFREQ_RELATION_H: return "CPUFREQ_RELATION_H";
+ default: return "relation ??";
+ }
+}
+
+static int cf750gx_target(struct cpufreq_policy *policy,
+ unsigned int target_freq, unsigned int relation)
+{
+unsigned int next_index = 0; /* Index into freq_table */
+unsigned int next_freq = 0; /* next frequency from perf table */
+unsigned int next_perf_state = 0; /* Index from perf table */
+int result = 0;
+unsigned int pll;
+unsigned int new_pll;
+unsigned int active_pll;
+struct cpufreq_freqs freqs;
+struct cpufreq_frequency_table *ft = cf750gx_v_f_table;
+
+ dprintk(__FILE__">%s(, %u KHz, relation %u)-%d: on cpu %d\n",
+ __func__, target_freq, relation, __LINE__, policy->cpu);
+
+ if (test_and_set_bit(cf750gxmChangingPllBit, &cf750gx_v_state_bits))
+ return -EAGAIN;
+
+ INIT_COMPLETION(cf750gx_v_exit_completion);
+
+ result = cpufreq_frequency_table_target(policy,
+ ft,
+ target_freq,
+ relation, &next_index);
+
+ if (unlikely(result))
+ goto cf750gxTargetNoFreq;
+
+ next_perf_state = ft[next_index].index;
+ next_freq = ft[next_index].frequency;
+ dprintk(__FILE__">%s()-%d: %d KHz (state=%x) selected from table "
+ "(%s)\n", __func__, __LINE__, next_freq, next_perf_state,
+ cf750gx_i_relation_str(relation));
+
+ pll = get_PLL();
+ active_pll = get_active_PLL(pll);
+
+#if 0
+#ifdef CONFIG_HOTPLUG_CPU
+ /* cpufreq holds the hotplug lock, so we are safe from here on */
+ cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
+#else
+ online_policy_cpus = policy->cpus;
+#endif
+#endif
+
+ if (pllif_pack_state(get_PLL_ratio(active_pll, pll), get_PLL_range(
+ active_pll, pll)) == next_perf_state) {
+ dprintk("Already at target state (%x)\n",
+ next_perf_state);
+ goto cf750gxTargetFreqSet;
+ }
+
+/* cpus_clear(cmd.mask); */
+
+ dprintk(__FILE__">%s()-%d: Current PLL: 0x%x\n", __func__, __LINE__,
+ pll);
+
+ if (active_pll) {
+ unsigned int current_state;
+
+ /*
+ * Since active PLL is 1, modify PLL 0. First see if it is
+ * already where we want it.
+ */
+ current_state = pllif_pack_state(get_PLL_ratio(0, pll),
+ get_PLL_range(0, pll));
+
+ dprintk(__FILE__">%s()-%d: pll 0 current state: 0x%x\n",
+ __func__, __LINE__, current_state);
+
+ if (current_state == next_perf_state) {
+ new_pll = PLL_DO_SEL<<24;
+ next_perf_state = 0;
+ } else {
+ next_perf_state = next_perf_state<<(PLL0_CFG_SHIFT-
+ PLL1_CFG_SHIFT);
+
+ new_pll = (PLL0_DO_CFG|PLL0_DO_RNG|PLL_DO_SEL)<<24;
+ }
+ } else {
+ unsigned int current_state;
+
+ /*
+ * Use PLL 1. Again, see if it is already at the desired
+ * configuration.
+ */
+ current_state = pllif_pack_state(get_PLL_ratio(1, pll),
+ get_PLL_range(1, pll));
+
+ dprintk(__FILE__">%s()-%d: pll 1 current state: 0x%x\n",
+ __func__, __LINE__, current_state);
+
+ if (current_state == next_perf_state) {
+ new_pll = (PLL_DO_SEL<<24)|PLL_SEL_MASK;
+ next_perf_state = 0;
+ } else {
+ new_pll = ((PLL1_DO_CFG|PLL1_DO_RNG|PLL_DO_SEL)<<24)|
+ PLL_SEL_MASK;
+ }
+ }
+
+ new_pll = new_pll|next_perf_state;
+
+ dprintk(__FILE__">%s()-%d: Modifying PLL: 0x%x\n", __func__, __LINE__,
+ new_pll);
+
+ freqs.old = pllif_cfg_to_freq(get_PLL_ratio(active_pll, pll))/1000;
+ freqs.new = ft[next_index].frequency;
+ freqs.cpu = 0;
+
+ cf750gx_v_switch_call_data.freqs = freqs;
+ cf750gx_v_switch_call_data.current_pll = new_pll;
+ cf750gx_v_switch_call_data.idle_pll_off = cf750gx_v_idle_pll_off;
+
+ cf750gx_v_lock_call_data.freqs = freqs;
+ cf750gx_v_lock_call_data.current_pll = new_pll;
+ cf750gx_v_lock_call_data.idle_pll_off = cf750gx_v_switch_call_data.
+ idle_pll_off;
+
+ dprintk(__FILE__">%s()-%d: freqs.old=%d, freqs.new=%d\n", __func__,
+ __LINE__, freqs.old, freqs.new);
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ result = pllif_modify_PLL(new_pll, 0);
+
+ if (result < 0)
+ goto cf750gxTargetUnlock;
+
+cf750gxTargetOut:
+ return result;
+
+cf750gxTargetNoFreq:
+ result = -ENODEV;
+
+ goto cf750gxTargetUnlock;
+cf750gxTargetFreqSet:
+ result = 0;
+
+ goto cf750gxTargetUnlock;
+cf750gxTargetUnlock:
+ clear_bit(cf750gxmChangingPllBit, &cf750gx_v_state_bits);
+ complete(&cf750gx_v_exit_completion);
+
+ goto cf750gxTargetOut;
+}
+
+static int cf750gx_verify(struct cpufreq_policy *policy)
+{
+ dprintk("%s()\n", __func__);
+
+ return cpufreq_frequency_table_verify(policy, cf750gx_v_f_table);
+}
+
+static int cf750gx_cpu_init(struct cpufreq_policy *policy)
+{
+unsigned int pll;
+unsigned int result = 0;
+
+ dprintk("%s()\n", __func__);
+
+ dprintk("policy->policy is %s (%d)\n", (policy->policy ==
+ CPUFREQ_POLICY_POWERSAVE || policy->policy ==
+ CPUFREQ_POLICY_PERFORMANCE)?(policy->policy ==
+ CPUFREQ_POLICY_POWERSAVE?"powersave":"performance"):
+ "undefined", policy->policy);
+
+ pll = get_PLL();
+
+ policy->cur = pllif_cfg_to_freq(get_PLL_ratio(get_active_PLL(pll),
+ pll))/1000;
+
+/* policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; */
+ policy->cpuinfo.transition_latency = pllif_get_latency();
+
+ result = cpufreq_frequency_table_cpuinfo(policy, cf750gx_v_f_table);
+ if (result)
+ goto err_freqfree;
+
+ cpufreq_frequency_table_get_attr(cf750gx_v_f_table, policy->cpu);
+
+ cf750gx_v_pll_switch_nb.notifier_call = cf750gx_pll_switch_cb;
+ cf750gx_v_pll_switch_nb.next = (struct notifier_block *)
+ &cf750gx_v_switch_call_data;
+ cf750gx_v_pll_switch_nb.priority = 0;
+
+ result = pllif_register_pll_switch_cb(&cf750gx_v_pll_switch_nb);
+
+ cf750gx_v_pll_lock_nb.notifier_call = cf750gx_pll_lock_cb;
+ cf750gx_v_pll_lock_nb.next =
+ (struct notifier_block *)&cf750gx_v_lock_call_data;
+ cf750gx_v_pll_lock_nb.priority = 0;
+
+ result = pllif_register_pll_lock_cb(&cf750gx_v_pll_lock_nb);
+
+ return result;
+
+err_freqfree:
+ return result;
+}
+
+static int cf750gx_cpu_exit(struct cpufreq_policy *policy)
+{
+ dprintk("%s()\n", __func__);
+
+ /*
+ * Wait for any active requests to ripple through before exiting
+ */
+ wait_for_completion(&cf750gx_v_exit_completion);
+
+ cpufreq_frequency_table_put_attr(policy->cpu);
+
+ pllif_unregister_pll_switch_cb(&cf750gx_v_pll_switch_nb);
+
+ pllif_unregister_pll_lock_cb(&cf750gx_v_pll_lock_nb);
+
+ cf750gx_v_pll_switch_nb.notifier_call = NULL;
+ cf750gx_v_pll_switch_nb.next = NULL;
+
+ cf750gx_v_pll_lock_nb.notifier_call = NULL;
+ cf750gx_v_pll_lock_nb.next = NULL;
+
+ return 0;
+}
+
+static int cf750gx_resume(struct cpufreq_policy *policy)
+{
+ return 0;
+}
+
+/*
+ * cf750gx_i_show_idle_pll_off - Show state of idle pll off boolean
+ */
+static ssize_t cf750gx_i_show_idle_pll_off(struct cpufreq_policy *policy,
+ char *buf)
+{
+ return sprintf(buf, "%d\n", cf750gx_v_idle_pll_off);
+}
+
+static ssize_t cf750gx_i_store_pll_off(struct cpufreq_policy *policy,
+ const char *buf, size_t count)
+{
+ if (buf[0] == '0')
+ cf750gx_v_idle_pll_off = 0;
+ else if (buf[0] == '1')
+ cf750gx_v_idle_pll_off = !0;
+
+ return 1;
+}
+
+static struct freq_attr idle_pll_off = {
+ .attr = { .name = "idle_pll_off",
+ .mode = 0644,
+ },
+ .show = cf750gx_i_show_idle_pll_off,
+ .store = cf750gx_i_store_pll_off,
+};
+
+/*
+ * cf750gx_i_show_min_max_mode - Show state of min max mode boolean
+ */
+static ssize_t cf750gx_i_show_min_max_mode(struct cpufreq_policy *policy,
+ char *buf)
+{
+ return sprintf(buf, "%d\n", cf750gx_v_min_max_mode);
+}
+
+static ssize_t cf750gx_i_store_min_max_mode(struct cpufreq_policy *policy,
+ const char *buf, size_t count)
+{
+int result;
+
+ if (buf[0] == '0') {
+ cf750gx_v_min_max_mode = 0;
+
+ cf750gx_v_f_table = cf750gx_v_freq_table;
+
+ cpufreq_frequency_table_put_attr(policy->cpu);
+
+ cpufreq_frequency_table_get_attr(cf750gx_v_freq_table,
+ policy->cpu);
+
+ result = cpufreq_frequency_table_cpuinfo(policy,
+ cf750gx_v_freq_table);
+ } else if (buf[0] == '1') {
+ cf750gx_v_min_max_mode = !0;
+
+ cf750gx_v_f_table = cf750gx_v_min_max_freq_table;
+
+ cpufreq_frequency_table_put_attr(policy->cpu);
+
+ cpufreq_frequency_table_get_attr(cf750gx_v_min_max_freq_table,
+ policy->cpu);
+
+ result = cpufreq_frequency_table_cpuinfo(policy,
+ cf750gx_v_min_max_freq_table);
+ }
+
+ return 1;
+}
+
+static struct freq_attr min_max_mode = {
+ .attr = { .name = "min_max_mode",
+ .mode = 0644,
+ },
+ .show = cf750gx_i_show_min_max_mode,
+ .store = cf750gx_i_store_min_max_mode,
+};
+
+
+static struct freq_attr *cf750gxvAttr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ &idle_pll_off,
+ &min_max_mode,
+ NULL,
+};
+
+static struct cpufreq_driver cf750gx_v_drv = {
+ .verify = cf750gx_verify,
+ .target = cf750gx_target,
+ .init = cf750gx_cpu_init,
+ .exit = cf750gx_cpu_exit,
+ .resume = cf750gx_resume,
+ .name = "ppc750gx-cpufreq",
+ .owner = THIS_MODULE,
+ .attr = cf750gxvAttr,
+};
+
+static int __init cf750gx_init(void)
+{
+int ret;
+unsigned int freq, i, j, rng, bus_clock;
+unsigned short min_ratio, max_ratio;
+struct cpufreq_frequency_table *tbp;
+const struct pll_750fgx_t *pll_defaults;
+
+ dprintk("%s()\n", __func__);
+
+ if (!cpu_has_feature(CPU_FTR_DUAL_PLL_750FX))
+ return 0;
+
+ /*
+ * Get processor min and max core frequencies. If they have not been
+ * overriden, then get them from version defaults.
+ */
+ if ((cur_cpu_spec->pvr_value>>16) == 0x7000)
+ pll_defaults = &pll_750fx;
+ else
+ pll_defaults = &pll_750gx;
+
+ cf750gx_v_min_core = override_min_core?override_min_core:pll_defaults->
+ min_core;
+ cf750gx_v_max_core = override_max_core?override_max_core:pll_defaults->
+ max_core;
+
+ dprintk(__FILE__">%s()-%d: cf750gx_v_min_core is %u, "
+ "cf750gx_v_max_core is %u\n", __func__, __LINE__,
+ cf750gx_v_min_core, cf750gx_v_max_core);
+ dprintk(__FILE__">%s()-%d: pll_defaults: min_ratio %d, max_ratio "
+ "%d\n", __func__, __LINE__, pll_defaults->min_ratio,
+ pll_defaults->max_ratio);
+
+ if (!cf750gx_v_min_core) {
+ dprintk("Can't determine minimum core frequency\n");
+ ret = -EINVAL;
+ goto ErrSimple;
+ }
+
+ if (!cf750gx_v_max_core) {
+ dprintk("Can't determine maximum core frequency\n");
+ ret = -EINVAL;
+ goto ErrSimple;
+ }
+
+ bus_clock = pllif_get_bus_clock()/1000;
+
+ /*
+ * Build maximum freq table. This will depend on the bus freq, the core
+ * frequency limits, and the ratios.
+ */
+ min_ratio = pll_defaults->min_ratio;
+ freq = min_ratio*bus_clock;
+
+ if (freq < cf750gx_v_min_core) {
+ /*
+ * Core min is above min ratio and bus speed clock. Find min
+ * ratio such that min ratio * bus speed >= core min.
+ */
+ min_ratio = cf750gx_v_min_core/bus_clock;
+ j = cf750gx_v_min_core%bus_clock;
+
+ if (j)
+ min_ratio++;
+ } else {
+ /*
+ * Core min is below min ratio and speed clock. Reset core min.
+ */
+ cf750gx_v_min_core = freq;
+ }
+
+ max_ratio = pll_defaults->max_ratio;
+ freq = max_ratio*bus_clock;
+
+ if (freq > cf750gx_v_max_core) {
+ /*
+ * Core max is below max ratio and bus speed. Find max ratio
+ * such that max ratio * bus speed <= core max.
+ */
+ max_ratio = cf750gx_v_max_core/bus_clock;
+ } else {
+ /*
+ * Core max is above max ratio and bus speed clock. Reset core
+ * max.
+ */
+ cf750gx_v_max_core = freq;
+ }
+
+ dprintk(__FILE__">%s()-%d: min_ratio is %d, max_ratio is %d\n",
+ __func__, __LINE__, min_ratio, max_ratio);
+
+ /*
+ * Bus ratios for the GX range from 2-20 for 19 INTEGER frequencies.
+ * The above checks may have changed this. There are max_ratio -
+ * min_ratio + 1 different frequencies.
+ */
+ j = max_ratio-min_ratio+1;
+ cf750gx_v_freq_table = kmalloc(sizeof(struct cpufreq_frequency_table)*
+ (j+5), GFP_KERNEL);
+ if (cf750gx_v_freq_table == NULL) {
+ ret = -ENOMEM;
+ goto ErrSimple;
+ }
+
+ dprintk(__FILE__">%s()-%d: cf750gx_v_freq_table=%p\n", __func__,
+ __LINE__, cf750gx_v_freq_table);
+
+ /*
+ * Use index of first entry to keep track of the count (one extra
+ * entry)
+ */
+ cf750gx_v_freq_table[0].frequency = CPUFREQ_ENTRY_INVALID;
+ cf750gx_v_freq_table[0].index = j;
+
+ /*
+ * Populate the table
+ */
+ for (tbp = cf750gx_v_freq_table+1, i = min_ratio; i <= max_ratio;
+ tbp++, i++) {
+ tbp->frequency = i*bus_clock;
+
+ /*
+ * I really don't know what the proper range values for 600 MHz
+ * and 900 MHz are? (The processor may also get pretty mad if
+ * you muck these up!)
+ */
+ if (tbp->frequency < 600000)
+ rng = 2;
+ else if (tbp->frequency < 900000)
+ rng = 0;
+ else
+ rng = 1;
+
+ /*
+ * The computation in the first argument converts the bus
+ * ratio value to the PLL configuration value needed for the
+ * given ratio
+ */
+ tbp->index = pllif_pack_state(i > 10?i+10:(i<<1), rng);
+
+ dprintk(__FILE__">%s()-%d: p->index=%x, ratio=%u, rng=%u\n",
+ __func__, __LINE__, tbp->index, i, rng);
+ }
+
+ /*
+ * 2nd extra array member
+ */
+ tbp->frequency = CPUFREQ_TABLE_END;
+
+ /*
+ * The other 3 extra array members are for the min max table.
+ */
+ cf750gx_v_min_max_freq_table = cf750gx_v_freq_table+
+ cf750gx_v_freq_table[0].index + 2;
+
+ cf750gx_v_min_max_freq_table[0] = cf750gx_v_freq_table[1];
+ cf750gx_v_min_max_freq_table[1] = cf750gx_v_freq_table[
+ cf750gx_v_freq_table[0].index];
+ cf750gx_v_min_max_freq_table[2].frequency = CPUFREQ_TABLE_END;
+
+ cf750gx_v_f_table = minmaxmode?cf750gx_v_min_max_freq_table:
+ cf750gx_v_freq_table;
+
+ ret = cpufreq_register_driver(&cf750gx_v_drv);
+
+ dprintk(__FILE__">%s()-%d: return from cpufreq_register_driver() is "
+ "%d\n", __func__, __LINE__, ret);
+
+ if (ret)
+ goto ErrFreqTable;
+
+ErrSimple:
+ return ret;
+ErrFreqTable:
+ kfree(cf750gx_v_freq_table);
+ return ret;
+}
+
+static void __exit cf750gx_exit(void)
+{
+ dprintk("%s()\n", __func__);
+
+ cpufreq_unregister_driver(&cf750gx_v_drv);
+
+ if (cf750gx_v_freq_table)
+ kfree(cf750gx_v_freq_table);
+
+ cf750gx_v_freq_table = cf750gx_v_min_max_freq_table =
+ cf750gx_v_f_table = NULL;
+
+ return;
+}
+
+module_param(override_max_core, uint, 0644);
+MODULE_PARM_DESC(override_max_core,
+ "clock frequency in KHz.");
+
+module_param(override_min_core, uint, 0644);
+MODULE_PARM_DESC(override_min_core,
+ "clock frequency in KHz.");
+
+module_param(minmaxmode, uint, 0644);
+MODULE_PARM_DESC(minmaxmode,
+ "Use only the minimum and maximum frequencies.");
+
+late_initcall(cf750gx_init);
+module_exit(cf750gx_exit);
+
+MODULE_ALIAS("dual-pll");
Index: arch/powerpc/kernel/cpu/Makefile
===================================================================
--- /dev/null 2004-08-10 18:55:00.000000000 -0700
+++ arch/powerpc/kernel/cpu/Makefile 2008-08-14 02:44:30.000000000 -0700
@@ -0,0 +1,6 @@
+#
+# Makefile for ppc CPU details and quirks
+#
+
+obj-$(CONFIG_CPU_FREQ) += cpufreq/
+obj-$(CONFIG_PPC_750GX_DUAL_PLL_IF) += pll_if.o