[PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Cyrill Gorcunov]

We should touch ESR register if only we have it.
The patch fixes the problem mentoined here

	http://lkml.org/lkml/2008/10/17/147

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
CC: Glauber Costa <glommer@gmail.com>
---

 arch/x86/kernel/smpboot.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Index: linux-2.6.git/arch/x86/kernel/smpboot.c
===================================================================
--- linux-2.6.git.orig/arch/x86/kernel/smpboot.c	2008-10-21 20:35:27.000000000 +0400
+++ linux-2.6.git/arch/x86/kernel/smpboot.c	2008-10-22 17:45:28.000000000 +0400
@@ -894,8 +894,10 @@ do_rest:
 		/*
 		 * Be paranoid about clearing APIC errors.
 	 	*/
-		apic_write(APIC_ESR, 0);
-		apic_read(APIC_ESR);
+		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
+			apic_write(APIC_ESR, 0);
+			apic_read(APIC_ESR);
+		}
 	}
 
 	/*

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Ingo Molnar]

* Cyrill Gorcunov <gorcunov@gmail.com> wrote:

> We should touch ESR register if only we have it.
> The patch fixes the problem mentoined here
> 
> 	http://lkml.org/lkml/2008/10/17/147
> 
> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
> CC: Glauber Costa <glommer@gmail.com>

> -		apic_write(APIC_ESR, 0);
> -		apic_read(APIC_ESR);
> +		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
> +			apic_write(APIC_ESR, 0);
> +			apic_read(APIC_ESR);
> +		}

i'm wondering - is the server there really that old, that it has no 
integrated lapic? I.e. it's an i486 SMP box or so? Or perhaps some 
other, weird SMP box?

	Ingo

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Glauber Costa]

On Wed, Oct 22, 2008 at 12:13 PM, Ingo Molnar <mingo@elte.hu> wrote:
>
> * Cyrill Gorcunov <gorcunov@gmail.com> wrote:
>
>> We should touch ESR register if only we have it.
>> The patch fixes the problem mentoined here
>>
>>       http://lkml.org/lkml/2008/10/17/147
>>
>> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
>> CC: Glauber Costa <glommer@gmail.com>
>
>> -             apic_write(APIC_ESR, 0);
>> -             apic_read(APIC_ESR);
>> +             if (APIC_INTEGRATED(apic_version[phys_apicid])) {
>> +                     apic_write(APIC_ESR, 0);
>> +                     apic_read(APIC_ESR);
>> +             }
>
> i'm wondering - is the server there really that old, that it has no
> integrated lapic? I.e. it's an i486 SMP box or so? Or perhaps some
> other, weird SMP box?

It's a Xeon, so probably just weird.

>
>        Ingo
>



-- 
Glauber  Costa.
"Free as in Freedom"
http://glommer.net

"The less confident you are, the more serious you have to act."

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Maciej W. Rozycki]

On Wed, 22 Oct 2008, Glauber Costa wrote:

> It's a Xeon, so probably just weird.

 The change would not affect it in any way then, because the condition is 
true.

  Maciej

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Cyrill Gorcunov]

[Ingo Molnar - Wed, Oct 22, 2008 at 04:13:54PM +0200]
| 
| * Cyrill Gorcunov <gorcunov@gmail.com> wrote:
| 
| > We should touch ESR register if only we have it.
| > The patch fixes the problem mentoined here
| > 
| > 	http://lkml.org/lkml/2008/10/17/147
| > 
| > Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| > CC: Glauber Costa <glommer@gmail.com>
| 
| > -		apic_write(APIC_ESR, 0);
| > -		apic_read(APIC_ESR);
| > +		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
| > +			apic_write(APIC_ESR, 0);
| > +			apic_read(APIC_ESR);
| > +		}
| 
| i'm wondering - is the server there really that old, that it has no 
| integrated lapic? I.e. it's an i486 SMP box or so? Or perhaps some 
| other, weird SMP box?
| 
| 	Ingo
| 

I was quite wondering too -- it's Xeon server.

>From http://lkml.org/lkml/2008/10/20/34
>> Hardware: Compaq P4 Xeon server, Broadcom CMIC-WS / CIOB-X2 board.
>> Tell me if you need more detailed information.

		- Cyrill -

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Ingo Molnar]

* Cyrill Gorcunov <gorcunov@gmail.com> wrote:

> | > -		apic_write(APIC_ESR, 0);
> | > -		apic_read(APIC_ESR);
> | > +		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
> | > +			apic_write(APIC_ESR, 0);
> | > +			apic_read(APIC_ESR);
> | > +		}
> | 
> | i'm wondering - is the server there really that old, that it has no 
> | integrated lapic? I.e. it's an i486 SMP box or so? Or perhaps some 
> | other, weird SMP box?
> | 
> | 	Ingo
> | 
> 
> I was quite wondering too -- it's Xeon server.
> 
> >From http://lkml.org/lkml/2008/10/20/34
> >> Hardware: Compaq P4 Xeon server, Broadcom CMIC-WS / CIOB-X2 board.
> >> Tell me if you need more detailed information.

ah, Compaq - how many CPUs does that box support? If it's 8 or more then 
perhaps they turned off the real local APIC, fudged some chipset glue to 
emulate APIC functionality and thus were able to use 8 or more of these 
chips? The built-in lapic would only go up to 4 CPUs. (or maybe even 
just up to dual, depending on the model)

This reminds us that all the is-integrated-lapic checks still matter 
today.

	Ingo

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Cyrill Gorcunov]

[Ingo Molnar - Wed, Oct 22, 2008 at 04:23:12PM +0200]
| 
| * Cyrill Gorcunov <gorcunov@gmail.com> wrote:
| 
| > | > -		apic_write(APIC_ESR, 0);
| > | > -		apic_read(APIC_ESR);
| > | > +		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
| > | > +			apic_write(APIC_ESR, 0);
| > | > +			apic_read(APIC_ESR);
| > | > +		}
| > | 
| > | i'm wondering - is the server there really that old, that it has no 
| > | integrated lapic? I.e. it's an i486 SMP box or so? Or perhaps some 
| > | other, weird SMP box?
| > | 
| > | 	Ingo
| > | 
| > 
| > I was quite wondering too -- it's Xeon server.
| > 
| > >From http://lkml.org/lkml/2008/10/20/34
| > >> Hardware: Compaq P4 Xeon server, Broadcom CMIC-WS / CIOB-X2 board.
| > >> Tell me if you need more detailed information.
| 
| ah, Compaq - how many CPUs does that box support? If it's 8 or more then 
| perhaps they turned off the real local APIC, fudged some chipset glue to 
| emulate APIC functionality and thus were able to use 8 or more of these 
| chips? The built-in lapic would only go up to 4 CPUs. (or maybe even 
| just up to dual, depending on the model)

I have no glue how many cpus it does supposrt :) Maybe Max know.

| 
| This reminds us that all the is-integrated-lapic checks still matter 
| today.
| 
| 	Ingo
| 
		- Cyrill -

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Ingo Molnar]

> > | > -		apic_write(APIC_ESR, 0);
> > | > -		apic_read(APIC_ESR);
> > | > +		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
> > | > +			apic_write(APIC_ESR, 0);
> > | > +			apic_read(APIC_ESR);
> > | > +		}

this wouldnt build with certain configs:

arch/x86/kernel/smpboot.c: In function 'do_boot_cpu':
arch/x86/kernel/smpboot.c:897: error: 'phys_apicid' undeclared (first use in this function)
arch/x86/kernel/smpboot.c:897: error: (Each undeclared identifier is reported only once
arch/x86/kernel/smpboot.c:897: error: for each function it appears in.)
include/asm/io_32.h: In function 'memcpy_fromio':

because phys_apicid is not available in the !WAKE_SECONDARY_VIA_INIT 
case. Changed it to boot_cpu_physical_apicid - that should be good 
enough.

	Ingo

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Cyrill Gorcunov]

[Ingo Molnar - Wed, Oct 22, 2008 at 04:59:09PM +0200]
| 
| > > | > -		apic_write(APIC_ESR, 0);
| > > | > -		apic_read(APIC_ESR);
| > > | > +		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
| > > | > +			apic_write(APIC_ESR, 0);
| > > | > +			apic_read(APIC_ESR);
| > > | > +		}
| 
| this wouldnt build with certain configs:
| 
| arch/x86/kernel/smpboot.c: In function 'do_boot_cpu':
| arch/x86/kernel/smpboot.c:897: error: 'phys_apicid' undeclared (first use in this function)
| arch/x86/kernel/smpboot.c:897: error: (Each undeclared identifier is reported only once
| arch/x86/kernel/smpboot.c:897: error: for each function it appears in.)
| include/asm/io_32.h: In function 'memcpy_fromio':
| 
| because phys_apicid is not available in the !WAKE_SECONDARY_VIA_INIT 
| case. Changed it to boot_cpu_physical_apicid - that should be good 
| enough.
| 
| 	Ingo
| 

Did you fixed it? (oh... actually I've been compilling the patch
but had this CONFIG turned on and didn't catch this issue)

		- Cyrill -

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Ingo Molnar]

* Cyrill Gorcunov <gorcunov@gmail.com> wrote:

> [Ingo Molnar - Wed, Oct 22, 2008 at 04:59:09PM +0200]
> | 
> | > > | > -		apic_write(APIC_ESR, 0);
> | > > | > -		apic_read(APIC_ESR);
> | > > | > +		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
> | > > | > +			apic_write(APIC_ESR, 0);
> | > > | > +			apic_read(APIC_ESR);
> | > > | > +		}
> | 
> | this wouldnt build with certain configs:
> | 
> | arch/x86/kernel/smpboot.c: In function 'do_boot_cpu':
> | arch/x86/kernel/smpboot.c:897: error: 'phys_apicid' undeclared (first use in this function)
> | arch/x86/kernel/smpboot.c:897: error: (Each undeclared identifier is reported only once
> | arch/x86/kernel/smpboot.c:897: error: for each function it appears in.)
> | include/asm/io_32.h: In function 'memcpy_fromio':
> | 
> | because phys_apicid is not available in the !WAKE_SECONDARY_VIA_INIT 
> | case. Changed it to boot_cpu_physical_apicid - that should be good 
> | enough.
> | 
> | 	Ingo
> | 
> 
> Did you fixed it? (oh... actually I've been compilling the patch
> but had this CONFIG turned on and didn't catch this issue)

yeah, fixed it up, dont worry about it.

	Ingo

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Cyrill Gorcunov]

[Ingo Molnar - Wed, Oct 22, 2008 at 05:04:16PM +0200]
| 
| * Cyrill Gorcunov <gorcunov@gmail.com> wrote:
| 
| > [Ingo Molnar - Wed, Oct 22, 2008 at 04:59:09PM +0200]
| > | 
| > | > > | > -		apic_write(APIC_ESR, 0);
| > | > > | > -		apic_read(APIC_ESR);
| > | > > | > +		if (APIC_INTEGRATED(apic_version[phys_apicid])) {
| > | > > | > +			apic_write(APIC_ESR, 0);
| > | > > | > +			apic_read(APIC_ESR);
| > | > > | > +		}
| > | 
| > | this wouldnt build with certain configs:
| > | 
| > | arch/x86/kernel/smpboot.c: In function 'do_boot_cpu':
| > | arch/x86/kernel/smpboot.c:897: error: 'phys_apicid' undeclared (first use in this function)
| > | arch/x86/kernel/smpboot.c:897: error: (Each undeclared identifier is reported only once
| > | arch/x86/kernel/smpboot.c:897: error: for each function it appears in.)
| > | include/asm/io_32.h: In function 'memcpy_fromio':
| > | 
| > | because phys_apicid is not available in the !WAKE_SECONDARY_VIA_INIT 
| > | case. Changed it to boot_cpu_physical_apicid - that should be good 
| > | enough.
| > | 
| > | 	Ingo
| > | 
| > 
| > Did you fixed it? (oh... actually I've been compilling the patch
| > but had this CONFIG turned on and didn't catch this issue)
| 
| yeah, fixed it up, dont worry about it.
| 
| 	Ingo
| 

Thanks Ingo!

		- Cyrill -

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Max Kellermann]

[-- Attachment #1: Type: text/plain, Size: 546 bytes --]

On 2008/10/22 16:23, Ingo Molnar <mingo@elte.hu> wrote:
> ah, Compaq - how many CPUs does that box support? If it's 8 or more then 
> perhaps they turned off the real local APIC, fudged some chipset glue to 
> emulate APIC functionality and thus were able to use 8 or more of these 
> chips? The built-in lapic would only go up to 4 CPUs. (or maybe even 
> just up to dual, depending on the model)

No, it's a rather small ProLiant server.  2 physical CPUs, maybe it
supports up to 4, but no more (each with HT).  I have attached its
dmesg.

Max

[-- Attachment #2: dmesg --]
[-- Type: text/plain, Size: 17863 bytes --]

BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 000000000009f400 (usable)
 BIOS-e820: 000000000009f400 - 00000000000a0000 (reserved)
 BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 000000007fffa000 (usable)
 BIOS-e820: 000000007fffa000 - 0000000080000000 (ACPI data)
 BIOS-e820: 00000000fec00000 - 00000000fec10000 (reserved)
 BIOS-e820: 00000000fee00000 - 00000000fee10000 (reserved)
 BIOS-e820: 00000000ffc00000 - 0000000100000000 (reserved)
last_pfn = 0x7fffa max_arch_pfn = 0x1000000
x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
kernel direct mapping tables up to 38000000 @ 7000-c000
DMI 2.3 present.
ACPI: RSDP 000F4F70, 0014 (r0 COMPAQ)
ACPI: RSDT 7FFFA000, 0030 (r1 COMPAQ P29             2   Ò\x04     162E)
ACPI: FACP 7FFFA040, 0074 (r1 COMPAQ P29             2   Ò\x04     162E)
ACPI: DSDT 7FFFA240, 3E50 (r1 COMPAQ     DSDT        1 MSFT  100000B)
ACPI: FACS 7FFFA0C0, 0040
ACPI: APIC 7FFFA100, 00AC (r1 COMPAQ 00000083        2             0)
ACPI: SPCR 7FFFA1C0, 0050 (r1 COMPAQ SPCRRBSU        1   Ò\x04     162E)
1151MB HIGHMEM available.
896MB LOWMEM available.
  mapped low ram: 0 - 38000000
  low ram: 00000000 - 38000000
  bootmap 00009000 - 00010000
(8 early reservations) ==> bootmem [0000000000 - 0038000000]
  #0 [0000000000 - 0000001000]   BIOS data page ==> [0000000000 - 0000001000]
  #1 [0000001000 - 0000002000]    EX TRAMPOLINE ==> [0000001000 - 0000002000]
  #2 [0000006000 - 0000007000]       TRAMPOLINE ==> [0000006000 - 0000007000]
  #3 [0000100000 - 00005e3ff0]    TEXT DATA BSS ==> [0000100000 - 00005e3ff0]
  #4 [00005e4000 - 00005ec000]    INIT_PG_TABLE ==> [00005e4000 - 00005ec000]
  #5 [000009f400 - 0000100000]    BIOS reserved ==> [000009f400 - 0000100000]
  #6 [0000007000 - 0000009000]          PGTABLE ==> [0000007000 - 0000009000]
  #7 [0000009000 - 0000010000]          BOOTMAP ==> [0000009000 - 0000010000]
found SMP MP-table at [c00f4fd0] 000f4fd0
Zone PFN ranges:
  DMA      0x00000000 -> 0x00001000
  Normal   0x00001000 -> 0x00038000
  HighMem  0x00038000 -> 0x0007fffa
Movable zone start PFN for each node
early_node_map[2] active PFN ranges
    0: 0x00000000 -> 0x0000009f
    0: 0x00000100 -> 0x0007fffa
On node 0 totalpages: 524185
free_area_init_node: node 0, pgdat c051e680, node_mem_map c1000000
  DMA zone: 3967 pages, LIFO batch:0
  Normal zone: 223520 pages, LIFO batch:31
  HighMem zone: 292602 pages, LIFO batch:31
ACPI: PM-Timer IO Port: 0x920
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] disabled)
ACPI: LAPIC (acpi_id[0x04] lapic_id[0x04] disabled)
ACPI: LAPIC (acpi_id[0x06] lapic_id[0x06] enabled)
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] disabled)
ACPI: LAPIC (acpi_id[0x05] lapic_id[0x05] disabled)
ACPI: LAPIC (acpi_id[0x07] lapic_id[0x07] enabled)
ACPI: LAPIC_NMI (acpi_id[0xff] dfl dfl lint[0x1])
ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
IOAPIC[0]: apic_id 2, version 17, address 0xfec00000, GSI 0-15
ACPI: IOAPIC (id[0x03] address[0xfec01000] gsi_base[16])
IOAPIC[1]: apic_id 3, version 17, address 0xfec01000, GSI 16-31
ACPI: IOAPIC (id[0x04] address[0xfec02000] gsi_base[32])
IOAPIC[2]: apic_id 4, version 17, address 0xfec02000, GSI 32-47
ACPI: IOAPIC (id[0x05] address[0xfec03000] gsi_base[48])
IOAPIC[3]: apic_id 5, version 17, address 0xfec03000, GSI 48-63
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 high edge)
ACPI: IRQ0 used by override.
ACPI: IRQ2 used by override.
ACPI: IRQ9 used by override.
Enabling APIC mode:  Flat.  Using 4 I/O APICs
Using ACPI (MADT) for SMP configuration information
mapped APIC to ffffb000 (fee00000)
mapped IOAPIC to ffffa000 (fec00000)
mapped IOAPIC to ffff9000 (fec01000)
mapped IOAPIC to ffff8000 (fec02000)
mapped IOAPIC to ffff7000 (fec03000)
Allocating PCI resources starting at 88000000 (gap: 80000000:7ec00000)
PERCPU: Allocating 39836 bytes of per cpu data
NR_CPUS: 8, nr_cpu_ids: 8, nr_node_ids 1
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 520089
Kernel command line: auto BOOT_IMAGE=Linux ro root=6801
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Initializing CPU#0
CPU 0 irqstacks, hard=c0585000 soft=c057d000
PID hash table entries: 4096 (order: 12, 16384 bytes)
TSC: PIT calibration confirmed by PMTIMER.
TSC: using PIT calibration value
Detected 2392.840 MHz processor.
Console: colour VGA+ 80x50
console [tty0] enabled
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 2073508k/2097128k available (2844k kernel code, 22436k reserved, 1451k data, 264k init, 1179624k highmem)
virtual kernel memory layout:
    fixmap  : 0xfff52000 - 0xfffff000   ( 692 kB)
    pkmap   : 0xffa00000 - 0xffc00000   (2048 kB)
    vmalloc : 0xf8800000 - 0xff9fe000   ( 113 MB)
    lowmem  : 0xc0000000 - 0xf8000000   ( 896 MB)
      .init : 0xc0538000 - 0xc057a000   ( 264 kB)
      .data : 0xc03c73e3 - 0xc0532150   (1451 kB)
      .text : 0xc0100000 - 0xc03c73e3   (2844 kB)
Checking if this processor honours the WP bit even in supervisor mode...Ok.
CPA: page pool initialized 1 of 1 pages preallocated
SLUB: Genslabs=12, HWalign=128, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
Calibrating delay loop (skipped), value calculated using timer frequency.. 4785.68 BogoMIPS (lpj=9571360)
Security Framework initialized
Mount-cache hash table entries: 512
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU0: Intel P4/Xeon Extended MCE MSRs (12) available
CPU0: Thermal monitoring enabled
Checking 'hlt' instruction... OK.
Freeing SMP alternatives: 13k freed
ACPI: Core revision 20080609
ENABLING IO-APIC IRQs
..TIMER: vector=0x31 apic1=0 pin1=2 apic2=-1 pin2=-1
CPU0: Intel(R) Xeon(TM) CPU 2.40GHz stepping 07
CPU 1 irqstacks, hard=c0586000 soft=c057e000
Booting processor 1/6 ip 6000
Initializing CPU#1
Calibrating delay using timer specific routine.. 4786.19 BogoMIPS (lpj=9572385)
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Physical Processor ID: 3
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#1.
CPU1: Intel P4/Xeon Extended MCE MSRs (12) available
CPU1: Thermal monitoring enabled
x86 PAT enabled: cpu 1, old 0x7040600070406, new 0x7010600070106
CPU1: Intel(R) Xeon(TM) CPU 2.40GHz stepping 07
checking TSC synchronization [CPU#0 -> CPU#1]: passed.
CPU 2 irqstacks, hard=c0587000 soft=c057f000
Booting processor 2/1 ip 6000
Initializing CPU#2
Calibrating delay using timer specific routine.. 4786.10 BogoMIPS (lpj=9572211)
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#2.
CPU2: Intel P4/Xeon Extended MCE MSRs (12) available
CPU2: Thermal monitoring enabled
x86 PAT enabled: cpu 2, old 0x7040600070406, new 0x7010600070106
CPU2: Intel(R) Xeon(TM) CPU 2.40GHz stepping 07
checking TSC synchronization [CPU#0 -> CPU#2]: passed.
CPU 3 irqstacks, hard=c0588000 soft=c0580000
Booting processor 3/7 ip 6000
Initializing CPU#3
Calibrating delay using timer specific routine.. 4786.21 BogoMIPS (lpj=9572434)
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Physical Processor ID: 3
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#3.
CPU3: Intel P4/Xeon Extended MCE MSRs (12) available
CPU3: Thermal monitoring enabled
x86 PAT enabled: cpu 3, old 0x7040600070406, new 0x7010600070106
CPU3: Intel(R) Xeon(TM) CPU 2.40GHz stepping 07
checking TSC synchronization [CPU#0 -> CPU#3]: passed.
Brought up 4 CPUs
Total of 4 processors activated (19144.19 BogoMIPS).
net_namespace: 596 bytes
NET: Registered protocol family 16
No dock devices found.
ACPI: bus type pci registered
PCI: Using configuration type 1 for base access
PCI: HP ProLiant DL380 detected, enabling pci=bfsort.
mtrr: your CPUs had inconsistent fixed MTRR settings
mtrr: probably your BIOS does not setup all CPUs.
mtrr: corrected configuration.
ACPI: EC: Look up EC in DSDT
ACPI: Interpreter enabled
ACPI: (supports S0 S5)
ACPI: Using IOAPIC for interrupt routing
ACPI: PCI Root Bridge [PCI0] (0000:00)
PCI: 0000:00:03.0 reg 10 32bit mmio: [f6000000, f6ffffff]
PCI: 0000:00:03.0 reg 14 io port: [2400, 24ff]
PCI: 0000:00:03.0 reg 18 32bit mmio: [f5ff0000, f5ff0fff]
PCI: 0000:00:03.0 reg 30 32bit mmio: [0, 1ffff]
pci 0000:00:03.0: supports D1
pci 0000:00:03.0: supports D2
PCI: 0000:00:04.0 reg 10 io port: [1800, 18ff]
PCI: 0000:00:04.0 reg 14 32bit mmio: [f5fe0000, f5fe01ff]
PCI: 0000:00:04.2 reg 10 io port: [2800, 28ff]
PCI: 0000:00:04.2 reg 14 32bit mmio: [f5fd0000, f5fd07ff]
PCI: 0000:00:04.2 reg 18 32bit mmio: [f5fc0000, f5fc1fff]
PCI: 0000:00:04.2 reg 1c 32bit mmio: [f5f00000, f5f7ffff]
PCI: 0000:00:04.2 reg 30 32bit mmio: [0, ffff]
pci 0000:00:04.2: PME# supported from D0 D3hot D3cold
pci 0000:00:04.2: PME# disabled
PCI: 0000:00:0f.1 reg 10 io port: [1f0, 1f7]
PCI: 0000:00:0f.1 reg 14 io port: [3f4, 3f7]
PCI: 0000:00:0f.1 reg 18 io port: [170, 177]
PCI: 0000:00:0f.1 reg 1c io port: [374, 377]
PCI: 0000:00:0f.1 reg 20 io port: [2000, 200f]
PCI: 0000:00:0f.2 reg 10 32bit mmio: [f5ef0000, f5ef0fff]
bus 00 -> node 0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Root Bridge [PCI1] (0000:01)
PCI: 0000:01:03.0 reg 10 64bit mmio: [f79c0000, f79fffff]
PCI: 0000:01:03.0 reg 18 io port: [3000, 30ff]
PCI: 0000:01:03.0 reg 1c 32bit mmio: [f78f0000, f78f3fff]
PCI: 0000:01:03.0 reg 30 32bit mmio: [0, 3fff]
pci 0000:01:03.0: supports D1
bus 01 -> node 0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI1._PRT]
ACPI: PCI Root Bridge [PCI2] (0000:02)
PCI: 0000:02:01.0 reg 10 64bit mmio: [f7af0000, f7afffff]
PCI: 0000:02:01.0 reg 30 32bit mmio: [0, ffff]
pci 0000:02:01.0: PME# supported from D3hot D3cold
pci 0000:02:01.0: PME# disabled
PCI: 0000:02:02.0 reg 10 64bit mmio: [f7ae0000, f7aeffff]
PCI: 0000:02:02.0 reg 30 32bit mmio: [0, ffff]
pci 0000:02:02.0: PME# supported from D3hot D3cold
pci 0000:02:02.0: PME# disabled
bus 02 -> node 0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI2._PRT]
ACPI: PCI Root Bridge [PCI3] (0000:03)
bus 03 -> node 0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI3._PRT]
ACPI: PCI Root Bridge [PCI4] (0000:06)
PCI: 0000:06:1e.0 reg 10 32bit mmio: [f7bf0000, f7bf0fff]
PCI: 0000:07:04.0 reg 10 32bit mmio: [f7ff0000, f7ff0fff]
PCI: 0000:07:04.0 reg 14 io port: [4000, 403f]
PCI: 0000:07:04.0 reg 18 32bit mmio: [f7e00000, f7efffff]
pci 0000:07:04.0: supports D1
pci 0000:07:04.0: supports D2
pci 0000:07:04.0: PME# supported from D0 D1 D2 D3hot
pci 0000:07:04.0: PME# disabled
PCI: 0000:07:05.0 reg 10 32bit mmio: [f7df0000, f7df0fff]
PCI: 0000:07:05.0 reg 14 io port: [4040, 407f]
PCI: 0000:07:05.0 reg 18 32bit mmio: [f7c00000, f7cfffff]
pci 0000:07:05.0: supports D1
pci 0000:07:05.0: supports D2
pci 0000:07:05.0: PME# supported from D0 D1 D2 D3hot
pci 0000:07:05.0: PME# disabled
PCI: bridge 0000:06:01.0 io port: [4000, 4fff]
PCI: bridge 0000:06:01.0 32bit mmio: [f7c00000, f7ffffff]
bus 06 -> node 0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI4._PRT]
ACPI: PCI Interrupt Link [IUSB] (IRQs 4 5 *7 10 11 15)
ACPI: PCI Interrupt Link [IN16] (IRQs 4 5 7 10 11 15) *3
ACPI: PCI Interrupt Link [IN17] (IRQs 4 *5 7 10 11 15)
ACPI: PCI Interrupt Link [IN18] (IRQs 4 5 7 10 11 *15)
ACPI: PCI Interrupt Link [IN19] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN20] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN21] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN22] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN23] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN24] (IRQs 4 5 7 10 *11 15)
ACPI: PCI Interrupt Link [IN25] (IRQs 4 5 *7 10 11 15)
ACPI: PCI Interrupt Link [IN26] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN27] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN28] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN29] (IRQs 4 5 7 10 *11 15)
ACPI: PCI Interrupt Link [IN30] (IRQs 4 5 7 *10 11 15)
ACPI: PCI Interrupt Link [IN31] (IRQs 4 5 7 10 11 *15)
ACPI: PCI Interrupt Link [IN32] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN33] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: PCI Interrupt Link [IN34] (IRQs 4 5 7 10 11 15) *0, disabled.
ACPI: WMI: Mapper loaded
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
ACPI: bus type pnp registered
pnp: PnP ACPI: found 13 devices
ACPI: ACPI bus type pnp unregistered
SCSI subsystem initialized
libata version 3.00 loaded.
PCI: Using ACPI for IRQ routing
system 00:01: ioport range 0xf50-0xf58 has been reserved
system 00:01: ioport range 0x408-0x40f has been reserved
system 00:01: ioport range 0x900-0x903 has been reserved
system 00:01: ioport range 0x910-0x911 has been reserved
system 00:01: ioport range 0x920-0x923 has been reserved
system 00:01: ioport range 0x930-0x937 has been reserved
system 00:01: ioport range 0x940-0x947 has been reserved
system 00:01: ioport range 0x950-0x957 has been reserved
system 00:01: ioport range 0xc06-0xc08 has been reserved
system 00:01: ioport range 0xc14-0xc14 has been reserved
system 00:01: ioport range 0xc49-0xc4a has been reserved
system 00:01: ioport range 0xc50-0xc52 has been reserved
system 00:01: ioport range 0xc6c-0xc6f has been reserved
system 00:01: ioport range 0x230-0x233 has been reserved
system 00:01: ioport range 0x260-0x267 has been reserved
system 00:01: ioport range 0x4d0-0x4d1 has been reserved
system 00:01: ioport range 0x700-0x70f has been reserved
system 00:01: ioport range 0x800-0x81f has been reserved
system 00:01: ioport range 0xc80-0xc83 has been reserved
system 00:01: ioport range 0xcd4-0xcd7 has been reserved
system 00:01: ioport range 0xcf9-0xcf9 could not be reserved
pci 0000:06:01.0: PCI bridge, secondary bus 0000:07
pci 0000:06:01.0:   IO window: 0x4000-0x4fff
pci 0000:06:01.0:   MEM window: 0xf7c00000-0xf7ffffff
pci 0000:06:01.0:   PREFETCH window: disabled
bus: 00 index 0 io port: [0, ffff]
bus: 00 index 1 mmio: [0, ffffffffffffffff]
bus: 01 index 0 io port: [0, ffff]
bus: 01 index 1 mmio: [0, ffffffffffffffff]
bus: 02 index 0 io port: [0, ffff]
bus: 02 index 1 mmio: [0, ffffffffffffffff]
bus: 03 index 0 io port: [0, ffff]
bus: 03 index 1 mmio: [0, ffffffffffffffff]
bus: 06 index 0 io port: [0, ffff]
bus: 06 index 1 mmio: [0, ffffffffffffffff]
bus: 07 index 0 io port: [4000, 4fff]
bus: 07 index 1 mmio: [f7c00000, f7ffffff]
bus: 07 index 2 mmio: [0, 0]
bus: 07 index 3 mmio: [0, 0]
NET: Registered protocol family 2
IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
TCP bind hash table entries: 65536 (order: 7, 524288 bytes)
TCP: Hash tables configured (established 131072 bind 65536)
TCP reno registered
NET: Registered protocol family 1
Machine check exception polling timer started.
highmem bounce pool size: 64 pages
SGI XFS with ACLs, security attributes, large block numbers, no debug enabled
msgmni has been set to 1747
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
pci 0000:00:03.0: Boot video device
pci 0000:07:04.0: Firmware left e100 interrupts enabled; disabling
pci 0000:07:05.0: Firmware left e100 interrupts enabled; disabling
input: Power Button (FF) as /class/input/input0
ACPI: Power Button (FF) [PWRF]
processor ACPI0007:00: registered as cooling_device0
processor ACPI0007:01: registered as cooling_device1
processor ACPI0007:06: registered as cooling_device2
processor ACPI0007:07: registered as cooling_device3
thermal LNXTHERM:01: registered as thermal_zone0
ACPI: Thermal Zone [THM0] (8 C)
Real Time Clock Driver v1.12ac
Serial: 8250/16550 driver4 ports, IRQ sharing disabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
00:07: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
Floppy drive(s): fd0 is 1.44M
FDC 0 is a National Semiconductor PC87306
loop: module loaded
HP CISS Driver (v 3.6.20)
cciss 0000:01:03.0: PCI INT A -> GSI 30 (level, low) -> IRQ 30
cciss0: <0xb178> at PCI 0000:01:03.0 IRQ 30 using DAC
      blocks= 71122560 block_size= 512
      heads=255, sectors=32, cylinders=8716

      blocks= 71122560 block_size= 512
      heads=255, sectors=32, cylinders=8716

 cciss/c0d0: p1 p2 p3 p4 < p5 p6 p7 p8 p9 >
      blocks= 142253280 block_size= 512
      heads=255, sectors=32, cylinders=17433

      blocks= 142253280 block_size= 512
      heads=255, sectors=32, cylinders=17433

 cciss/c0d1: p1
tun: Universal TUN/TAP device driver, 1.6
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
Loading iSCSI transport class v2.0-870.
Driver 'sd' needs updating - please use bus_type methods
Driver 'sr' needs updating - please use bus_type methods
scsi0 : pata_serverworks
scsi1 : pata_serverworks
ata1: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x2000 irq 14
ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x2008 irq 15
Switched to high resolution mode on CPU 1
Switched to high resolution mode on CPU 3
Switched to high resolution mode on CPU 2
Switched to high resolution mode on CPU 0

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Maciej W. Rozycki]

On Wed, 22 Oct 2008, Ingo Molnar wrote:

> ah, Compaq - how many CPUs does that box support? If it's 8 or more then 
> perhaps they turned off the real local APIC, fudged some chipset glue to 
> emulate APIC functionality and thus were able to use 8 or more of these 
> chips? The built-in lapic would only go up to 4 CPUs. (or maybe even 
> just up to dual, depending on the model)

 Hmm, interesting.  The integrated APIC should support up to 14 CPUs 
(assuming one ID is needed for the I/O APIC).  One cannot preclude silicon 
errata affecting the less common hardware configurations though.  It would 
be interesting to see a full bootstrap log with all the APIC debug 
information enabled.  That would probably clarify matters a bit.

 Note that Compaq would have to come with their own solution about the 
discrete APIC as the 82489DX went out of production many years ago -- ten 
at the very least.  OTOH, they could have stockpiled them back then. ;)  
This is one of the few manufacturers I would actually suspect doing so as 
they always seemed keen on going SMP.  Good to know we can support these 
boxes at all these days.

> This reminds us that all the is-integrated-lapic checks still matter 
> today.

 Quite surprising indeed.

  Maciej

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Maciej W. Rozycki]

On Wed, 22 Oct 2008, Ingo Molnar wrote:

> i'm wondering - is the server there really that old, that it has no 
> integrated lapic? I.e. it's an i486 SMP box or so? Or perhaps some 
> other, weird SMP box?

 I've been wondering about that too, though the fix is correct either way.  

 Note that all the discrete APIC boxes we have ever supported were 
Pentium-based, either the original P5 (i.e. 60/66MHz) chips which had no 
APIC on chip at all or P54C ones but with the integrated APIC disabled 
(because the systems were 4-way SMP or suchlike and there was no suitable 
chipset component to provide a compatible I/O APIC).

 All the documentation for i486 SMP boxes I was able to track down 
indicated that even if APIC chips were used with them, the whole setup did 
not support the MP table as defined by the MultiProcessor Specification 
and therefore could not be supported by Linux as it is.  And I have never 
come across a specimen to look into it any further.

  Maciej

Re: [PATCH -tip] x86: do_boot_cpu - check if we have ESR register

[Maciej W. Rozycki]

On Wed, 22 Oct 2008, Cyrill Gorcunov wrote:

> We should touch ESR register if only we have it.
> The patch fixes the problem mentoined here
> 
> 	http://lkml.org/lkml/2008/10/17/147
> 
> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
> CC: Glauber Costa <glommer@gmail.com>
> ---

Acked-by: Maciej W. Rozycki <macro@linux-mips.org>

 Note this is one of the few places you can actually write to the ESR 
unconditionally -- there is another similar piece of code elsewhere in 
this file which could get adjusted to look the same as this one after your 
change.  Thanks for this fix.

  Maciej