Needed by architecture-independant tsc-sync.c. Signed-off-by: Mathieu Desnoyers CC: Ralf Baechle CC: Peter Zijlstra --- arch/mips/include/asm/barrier.h | 6 ++++++ 1 file changed, 6 insertions(+) Index: linux.trees.git/arch/mips/include/asm/barrier.h =================================================================== --- linux.trees.git.orig/arch/mips/include/asm/barrier.h 2008-11-12 18:15:47.000000000 -0500 +++ linux.trees.git/arch/mips/include/asm/barrier.h 2008-11-26 06:57:50.000000000 -0500 @@ -152,4 +152,10 @@ #define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") #define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +/* + * MIPS does not have any instruction to serialize instruction execution on the + * core. + */ +#define sync_core() + #endif /* __ASM_BARRIER_H */ -- Mathieu Desnoyers OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68