[PATCH] x86: change the default cache size to 64 bytes

[PATCH] x86: change the default cache size to 64 bytes

[Ingo Molnar]

>From 632c5045d6827a3d044b6eb216d0e5597b25d468 Mon Sep 17 00:00:00 2001
From: Ingo Molnar <mingo@elte.hu>
Date: Mon, 12 Jan 2009 23:37:16 +0100
Subject: [PATCH] x86: change the default cache size to 64 bytes

Right now the generic cacheline size is 128 bytes - that is wasteful
when structures are aligned, as all modern x86 CPUs have an (effective)
cacheline sizes of 64 bytes.

It was set to 128 bytes due to some cacheline aliasing problems on
older P4 systems, but those are many years old and we dont optimize
for them anymore. (They'll still get the 128 bytes cacheline size if
the kernel is specifically built for Pentium 4)

Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 arch/x86/Kconfig.cpu |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 8078955..cdf4a96 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -307,10 +307,10 @@ config X86_CMPXCHG
 
 config X86_L1_CACHE_SHIFT
 	int
-	default "7" if MPENTIUM4 || X86_GENERIC || GENERIC_CPU || MPSC
+	default "7" if MPENTIUM4 || MPSC
 	default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
 	default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
-	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7
+	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7 || X86_GENERIC || GENERIC_CPU
 
 config X86_XADD
 	def_bool y

Re: [PATCH] x86: change the default cache size to 64 bytes

[Arjan van de Ven]

On Mon, 12 Jan 2009 23:44:28 +0100
Ingo Molnar <mingo@elte.hu> wrote:

> >From 632c5045d6827a3d044b6eb216d0e5597b25d468 Mon Sep 17 00:00:00
> >2001
> From: Ingo Molnar <mingo@elte.hu>
> Date: Mon, 12 Jan 2009 23:37:16 +0100
> Subject: [PATCH] x86: change the default cache size to 64 bytes
> 
> Right now the generic cacheline size is 128 bytes - that is wasteful
> when structures are aligned, as all modern x86 CPUs have an
> (effective) cacheline sizes of 64 bytes.
> 
> It was set to 128 bytes due to some cacheline aliasing problems on
> older P4 systems, but those are many years old and we dont optimize
> for them anymore. (They'll still get the 128 bytes cacheline size if
> the kernel is specifically built for Pentium 4)
> 
> Signed-off-by: Ingo Molnar <mingo@elte.hu>

Acked-by: Arjan van de Ven <arjan@linux.intel.com>


-- 
Arjan van de Ven 	Intel Open Source Technology Centre
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