[patch 05/56] agp/intel: Reduce extraneous PCI posting reads during init

Greg KH
2009-02-11T00:29:48Z

[-- Attachment #1: agp-intel-reduce-extraneous-pci-posting-reads-during-init.patch --]
[-- Type: text/plain, Size: 2026 bytes --]

2.6.27-stable review patch. If anyone has any objections, please let us know.
------------------

From: Keith Packard <keithp@keithp.com>

commit 44d494417278e49f5b42bd3ded1801b6d2254db8 upstream.

Instead of doing a posting read after each GTT entry update, do a single one
at the end of the writes. This should reduce boot time a tiny amount by
avoiding a lot of extra uncached reads.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

---
drivers/char/agp/intel-agp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -217,8 +217,8 @@ static int intel_i810_configure(void)
if (agp_bridge->driver->needs_scratch_page) {
for (i = 0; i < current_size->num_entries; i++) {
writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
- readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
}
+ readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
}
global_cache_flush();
return 0;
@@ -778,8 +778,8 @@ static int intel_i830_configure(void)
if (agp_bridge->driver->needs_scratch_page) {
for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
- readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
}
+ readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
}

global_cache_flush();
@@ -994,8 +994,8 @@ static int intel_i915_configure(void)
if (agp_bridge->driver->needs_scratch_page) {
for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
writel(agp_bridge->scratch_page, intel_private.gtt+i);
- readl(intel_private.gtt+i); /* PCI Posting. */
}
+ readl(intel_private.gtt+i-1); /* PCI Posting. */
}

global_cache_flush();