[PATCH] Enable GART-IOMMU only after setting up protection methods

[Mark Langsdorf <mark.langsdorf@amd.com>]

The current code to set up the GART as an IOMMU enables GART
translations before it removes the aperture from the kernel
memory map, sets the GART PTEs to UC, sets up the guard and
scratch pages, or does a wbinvd().  This leaves the possibility
of cache aliasing open and can cause system crashes.

Re-order the code and add tlbflush so as to enable the 
GART translations only after all safeguards are in place and
the tlb has been flushed.

AMD has tested this patch and seen no adverse effects.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>

diff -r 0d1744c7acc7 arch/x86/kernel/pci-gart_64.c
--- a/arch/x86/kernel/pci-gart_64.c	Fri Mar 27 16:47:28 2009 -0500
+++ b/arch/x86/kernel/pci-gart_64.c	Mon Mar 30 15:05:47 2009 -0500
@@ -38,6 +38,7 @@
 #include <asm/swiotlb.h>
 #include <asm/dma.h>
 #include <asm/k8.h>
+#include <asm/tlbflush.h>
 
 static unsigned long iommu_bus_base;	/* GART remapping area (physical) */
 static unsigned long iommu_size;	/* size of remapping area bytes */
@@ -682,9 +683,9 @@
 	if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
 		panic("Could not set GART PTEs to uncacheable pages");
 
+	wbinvd();
+
 	agp_gatt_table = gatt;
-
-	enable_gart_translations();
 
 	error = sysdev_class_register(&gart_sysdev_class);
 	if (!error)
@@ -855,6 +856,11 @@
 	for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
 		iommu_gatt_base[i] = gart_unmapped_entry;
 
+	wbinvd();
+	flush_tlb_all();
+
+	enable_gart_translations();
+
 	flush_gart();
 	dma_ops = &gart_dma_ops;
 }