Re: [PATCH] x86: cacheinfo: complete L2/L3 Cache and TLB associativity field definitions

Ingo Molnar
2009-04-02T10:30:40Z

* Andreas Herrmann <andreas.herrmann3@amd.com> wrote:

> Impact: complete cache information for AMD CPUs
>
> See "CPUID Specification" (AMD Publication #: 25481, Rev. 2.28, April 2008)
>
> Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
> ---
> arch/x86/kernel/cpu/intel_cacheinfo.c | 16 ++++++++++++----
> 1 files changed, 12 insertions(+), 4 deletions(-)
>
> Please apply.

Hm, the x86/cpu topic is marked broken and blocked by another AMD
patch from Mark Langsdorf:

45ca863: x86, cpu: conform L3 Cache Index Disable to Linux standards

We cannot queue up new patches there before this one is fixed. I've
attached below my last bugreport about it.

Ingo

----- Forwarded message from Ingo Molnar <mingo@elte.hu> -----

Date: Thu, 19 Mar 2009 09:18:37 +0100
From: Ingo Molnar <mingo@elte.hu>
To: Mark Langsdorf <mark.langsdorf@amd.com>
Subject: Re: [PATCH][retry 5] Conform L3 Cache Index Disable to Linux
Standards
Cc: Andrew Morton <akpm@linux-foundation.org>, linux-kernel@vger.kernel.org,
eric@lammerts.org, hpa@zytor.com

* Mark Langsdorf <mark.langsdorf@amd.com> wrote:

> Add ABI Documentation entry and fix some /sys directory formating
> issues with the L3 Cache Index Disable feature for future AMD
> processors. Add a check to disable it for family 0x10 models
> that do not support it properly. Correct the disable algorithm
> to reflect erratum 388.
>
> Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>

i'm still getting this build failure:

arch/x86/mm/built-in.o:(.bss+0x3640): multiple definition of `k8_northbridges'

i've reported this build failure before. I've excluded this commit
from tip:master for now.

Ingo

----- End forwarded message -----