Re: [spi-devel-general] [PATCH v2] spi: Add support for the OpenCores SPI controller.

[Thierry Reding <thierry.reding@avionic-design.de>]

* David Brownell wrote:
> On Tuesday 28 April 2009, Florian Fainelli wrote:
> > > > Is this the http://www.opencores.org/?do=project&who=spi core?
> > >
> > > Yes, it is.
> > >
> > > > Its summary says "Variable length of transfer word up to 32 bits";
> > > > does that mean "configurable when core is synthesized" instead of
> > > > truly "variable"?
> > 
> > This is indeed configured at synthesis time.
> 
> Now I'm confused again.  Thierry says (below) that the number of bits
> can be set per-"transfer".
> 
> Now, I can easily understand that a *maximum* would be configured
> at synthesis time ... if there's a 32-bit CPU or DMA engine, it'd
> make very limited sense to interact using 128-bit I/O words.

I can't really comment on the synthesis because I'm not involved with that
part. What I was saying that the core provides a field in the control
register which defines the number of bits to transfer from/to the
transmit/receive registers. The maximum number of bits that can be specified
in this way is 128.

> Is there both a configurable maximum, *and* a word-size setting that
> can be changed on the fly?  That's what I would expect; it's what
> most other designs do.  The only time I've seen fixed "you must use
> N-bit words" designs is on cost-eradicated 8-bit microcontrollers.

Perhaps that maximum number of bits that can be set through the control
register is what can be configured at synthesis time.

> - Dave

Thierry