Re: [spi-devel-general] [PATCH v2] spi: Add support for the OpenCores SPI controller.

[Florian Fainelli <florian@openwrt.org>]

Le Wednesday 29 April 2009 08:31:04 Thierry Reding, vous avez écrit :
> * David Brownell wrote:
> > On Tuesday 28 April 2009, Florian Fainelli wrote:
> > > > > Is this the http://www.opencores.org/?do=project&who=spi core?
> > > >
> > > > Yes, it is.
> > > >
> > > > > Its summary says "Variable length of transfer word up to 32 bits";
> > > > > does that mean "configurable when core is synthesized" instead of
> > > > > truly "variable"?
> > >
> > > This is indeed configured at synthesis time.
> >
> > Now I'm confused again.  Thierry says (below) that the number of bits
> > can be set per-"transfer".
> >
> > Now, I can easily understand that a *maximum* would be configured
> > at synthesis time ... if there's a 32-bit CPU or DMA engine, it'd
> > make very limited sense to interact using 128-bit I/O words.

The maximum size of the FIFO is configured at synthesis time should have made 
this clear before, sorry for the confusion.

>
> I can't really comment on the synthesis because I'm not involved with that
> part. What I was saying that the core provides a field in the control
> register which defines the number of bits to transfer from/to the
> transmit/receive registers. The maximum number of bits that can be
> specified in this way is 128.

Yes, which matches the FIFO size configured in the IP at synthesis time.

>
> > Is there both a configurable maximum, *and* a word-size setting that
> > can be changed on the fly?  That's what I would expect; it's what
> > most other designs do.  The only time I've seen fixed "you must use
> > N-bit words" designs is on cost-eradicated 8-bit microcontrollers.
>
> Perhaps that maximum number of bits that can be set through the control
> register is what can be configured at synthesis time.

Provided that your FIFO is 128-bits, you can of course ask the core to do up 
to the FIFO-size transfers for instance provided that you do not exceed the 
size of the FIFO. The later can obviously not be changed on-the-fly since 
physical resources of the FPGA for this should be reserved at synthesis time. 
Of course, one could use partial reconfiguration to increase the size, but 
that's slightly off-topic ;)
-- 
Best regards, Florian Fainelli
Email : florian@openwrt.org
http://openwrt.org
-------------------------------