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Date: Thu, 30 Apr 2009 19:23:41 +0200
From: Ingo Molnar <mingo@elte.hu>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Christoph Lameter <cl@linux.com>,
       Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>,
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       ltt-dev@lists.casi.polymtl.ca, Tejun Heo <tj@kernel.org>
Subject: Re: [PATCH] Fix dirty page accounting in
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* Linus Torvalds <torvalds@linux-foundation.org> wrote:

> On Thu, 30 Apr 2009, Ingo Molnar wrote:
> > 
> > c0436275:   64 83 05 20 5f 6a c0    addl   $0x1,%fs:0xc06a5f20
> > 
> > There's no atomic instructions at all - the counters here are 
> > only accessed locally. They are local-irq-atomic, but not 
> > cacheline-atomic.
> 
> On other architectures, you need the whole "disable preemption, 
> load-locked, store-conditional, test-and-loop, enable preemption" 
> thing.
> 
> Or "disable interrupts, load, store, restore interrupts".
> 
> There really aren't very many architectures that can do almost 
> unrestricted ALU ops in a single instruction (and thus 
> automatically safe from preemption and interrupts).

Maybe then what we should do is the very first version of commit 
6dbde35308: declaredly make percpu_arith_op() non-irq-atomic (and 
non-preempt-atomic) everywhere. The commit's internal changelog 
still says:

        * made generic percpu ops atomic against preemption

So we introduced preemption-safety in the v2 version of that commit.

This non-atomicity will 1) either not matter 2) will be irq-atomic 
by virtue of being within a critical section 3) can be made atomic 
in the few remaining cases.

And maybe, at most, introduce an opt-in API: percpu_add_irqsafe().

Right?

	Ingo