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Date: Fri, 1 May 2009 09:53:11 +0200
From: Borislav Petkov <petkovbb@googlemail.com>
To: Aristeu Rozanski <aris@redhat.com>
Cc: Andi Kleen <andi@firstfloor.org>,
       Borislav Petkov <borislav.petkov@amd.com>, akpm@linux-foundation.org,
       greg@kroah.com, mingo@elte.hu, tglx@linutronix.de, hpa@zytor.com,
       dougthompson@xmission.com, linux-kernel@vger.kernel.org,
       Ben Woodard <woodard@redhat.com>,
       Mauro Carvalho Chehab <mchehab@redhat.com>
Subject: Re: [RFC PATCH 00/21 v2] amd64_edac: EDAC module for AMD64
Message-ID: <20090501075311.GA14176@liondog.tnic>
Reply-To: petkovbb@gmail.com
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	Andi Kleen <andi@firstfloor.org>,
	Borislav Petkov <borislav.petkov@amd.com>,
	akpm@linux-foundation.org, greg@kroah.com, mingo@elte.hu,
	tglx@linutronix.de, hpa@zytor.com, dougthompson@xmission.com,
	linux-kernel@vger.kernel.org, Ben Woodard <woodard@redhat.com>,
	Mauro Carvalho Chehab <mchehab@redhat.com>
References: <1241024107-14535-1-git-send-email-borislav.petkov@amd.com> <87iqknp8a0.fsf@basil.nowhere.org> <20090430115741.GA23634@aftab> <20090430124716.GW23223@one.firstfloor.org> <20090430144756.GA25200@redhat.com>
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Hi all,

I thought I should summarize some points on the design direction, which,
in my impression are what all the parties involved more or less would
agree on:

* mce interrupt delivers, if EDAC compiled in, the required batch of
dumped MSRs to chipset/CPU specific EDAC driver. Aristeu, I guess you
guys have some code on that, right?

* EDAC module decodes MCE info, computes the DIMM label out of
that. Additional hw setup stuff like memory hoisting/interleaving,
ganged/unganged MC mode, testing infrastructure like DRAM error
injection and all that pertaining to the specific hw is handled by the
EDAC module.

* If EDAC not enabled, mce operates as before.

Comments/suggestions?

Hit me! :)

-- 
Regards/Gruss,
    Boris.