From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1765426AbZEAUYR (ORCPT ); Fri, 1 May 2009 16:24:17 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1757449AbZEAUYF (ORCPT ); Fri, 1 May 2009 16:24:05 -0400 Received: from tomts43.bellnexxia.net ([209.226.175.110]:60853 "EHLO tomts43-srv.bellnexxia.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752922AbZEAUYE (ORCPT ); Fri, 1 May 2009 16:24:04 -0400 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AugEAOvw+klMQW1W/2dsb2JhbACBUM4eg30F Date: Fri, 1 May 2009 16:24:00 -0400 From: Mathieu Desnoyers To: Christoph Lameter Cc: Nick Piggin , Peter Zijlstra , Linux Kernel Mailing List , Yuriy Lalym , ltt-dev@lists.casi.polymtl.ca, Tejun Heo , Ingo Molnar , Linus Torvalds , Andrew Morton Subject: Re: [ltt-dev] [PATCH] Fix dirty page accounting in redirty_page_for_writepage() Message-ID: <20090501202400.GA20280@Krystal> References: <20090430065055.GA16277@elte.hu> <20090430141211.GB5922@Krystal> <20090430194158.GB12926@Krystal> <20090430211750.GA19933@Krystal> <20090501192142.GA18339@Krystal> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Disposition: inline In-Reply-To: X-Editor: vi X-Info: http://krystal.dyndns.org:8080 X-Operating-System: Linux/2.6.21.3-grsec (i686) X-Uptime: 16:16:03 up 62 days, 16:42, 2 users, load average: 0.63, 0.87, 0.67 User-Agent: Mutt/1.5.18 (2008-05-17) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Christoph Lameter (cl@linux.com) wrote: > On Fri, 1 May 2009, Mathieu Desnoyers wrote: > > > What I do here is to let those u8 counters increment as free-running > > counters. Yes, they will periodically overflow the 8 bits. But I don't > > rely on this for counting the number of increments we need between > > global counter updates : I use the bitmask taken from the threshold > > value (which is now required to be a power of two) to detect 0, 1, 2, 3, > > 4, 5, 6 or 7-bit counter overflow. Therefore we can still have the kind > > of granularity currently provided. The only limitation is that we have > > to use powers of two for the threshold, so we end up counting in power > > of two modulo, which will be unaffected by the u8 overflow. > > Ack. Got it. Looks good. > Super ! :) So, back to my original point : do you agree on the usefulness of separating fallback irq-disabling from the per-cpu atomic construct ? e.g. : __inc_zone_state percpu_add_return_irq(var); inc_zone_state percpu_irqsave(flags); __inc_zone_state() percpu_irqrestore(flags); This would require that percpu_add_return_irq should always be called either in : - irq disabled code paths - in code paths surrounded by percpu_irqsave/restore. In this example : x86 would map : percpu_irqsave/restore to "nothing". percpu_add_return_irq to xadd instruction. It is irq-safe by design. Other architectures (fallback) would map percpu_irqsave/restore to local_irq_save/restore. percpu_add_return_irq to var += value; return var; Mathieu -- Mathieu Desnoyers OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68