Re: Broken ARM atomic ops wrt memory barriers (was : [PATCH] Add cmpxchg support for ARMv6+ systems)

[Jamie Lokier <jamie@shareable.org>]

Mathieu Desnoyers wrote:
> I use a local cmpxchg in the LTTng tree as key instruction to manage the
> ring buffer in a irq, softirq and NMI-safe way (due to the atomic nature
> of this instruction), but without the overhead of synchronizing across
> CPUs.
> 
> On ARM, the semantic looks a bit like PowerPC with linked load/linked
> store, and you don't seem to need memory barriers. I guess that's either
> because
> 
> a) they are implicit in the ll/ls or
> b) ARM does not perform out-of-order memory read/writes or
> c) they've simply been forgotten, and it's a bug.
> 
> the cmpxchg local instruction maps currently to cmpxchg, as a fallback,
> since there is no difference between the SMP-aware and UP-only
> instructions.
> 
> But if I look at arch/arm/include/asm/spinlock.h, the answer I get seems
> to be c) : ARM needs memory barriers.

Memory barriers only affect the observed access order with respect to
other processors (and perhaps other devices).

So a CPU-local operation would not need barriers.  CPU-local code,
including local IRQs, see all memory accesses in the same order as
executed instructions.

Of course you need barriers at some point, when using the local data
to update global data seen by other CPUs at a later time.  But that is
hopefully done elsewhere.

After considering this, do you think it's still missing barriers?

-- Jamie