Re: Linux 2.6.30-rc8 [also: VIA Support]

["Michael S. Zick" <lkml@morethan.org>]

On Thu June 4 2009, Dave Jones wrote:
> On Thu, Jun 04, 2009 at 04:01:30PM -0500, Michael S. Zick wrote:
> 
>  > But while your here, what is your opinion on this one,
>  > in: int __init pcibios_init(void)
>  > 
>  > - - - - -
>  >         pci_cache_line_size = 32 >> 2;
>  >         if (c->x86 >= 6
>  >         && (c->x86_vendor == X86_VENDOR_AMD) || (c->x86_vendor == X86_VENDOR_CENTAUR))
>  >                 pci_cache_line_size = 64 >> 2;  /* K7 & K8 and VIA C7-M */
>  >         else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
>  >                 pci_cache_line_size = 128 >> 2; /* P4 */
>  > 
>  > Mike
> 
> C7's L1 cachelines are 64 bytes, so it's right in that case,
> but the earlier Centaur CPUs are 32 bytes, so it should be checking steppings.
> 
> Or better yet, why not just set it to boot_cpu_data->x86_clflush_size ?
> 

I have already preceded that chunk of code with a printk and confirmed
that x86_clflush_size is properly set to 64 bytes (somewhere else).

So your suggestion is the obvious one for the C7-M,
I don't know about any other makes/models. 

This machine's C7-M is being reported as a "stepping 0" ??
What is earlier than a stepping 0 ??

Mike

> 	Dave
> 
> 
>