[PATCH -tip] perf_counter/x86: Fix the model number of Intel Core2 processors

[PATCH -tip] perf_counter/x86: Fix the model number of Intel Core2 processors

[Yong Wang]

Fix the model number of Intel Core2 processors according to the documentation
Intel Processor Identification with the CPUID Instruction
http://www.intel.com/support/processors/sb/cs-009861.htm

Signed-off-by: Yong Wang <yong.y.wang@intel.com>

---
 arch/x86/kernel/cpu/perf_counter.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 40978aa..a49a82c 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -1407,7 +1407,8 @@ static int intel_pmu_init(void)
 	 * Install the hw-cache-events table:
 	 */
 	switch (boot_cpu_data.x86_model) {
-	case 17:
+	case 15:
+	case 23:
 		memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 

[tip:perfcounters/core] perf_counter/x86: Fix the model number of Intel Core2 processors

[tip-bot for Yong Wang]

Commit-ID:  232f61fa1da4ec7e1aa3d7ca6444f3a436941d36
Gitweb:     http://git.kernel.org/tip/232f61fa1da4ec7e1aa3d7ca6444f3a436941d36
Author:     Yong Wang <yong.y.wang@linux.intel.com>
AuthorDate: Wed, 10 Jun 2009 17:06:12 +0800
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Wed, 10 Jun 2009 12:34:24 +0200

perf_counter/x86: Fix the model number of Intel Core2 processors

Fix the model number of Intel Core2 processors according to the
documentation: Intel Processor Identification with the CPUID
Instruction: http://www.intel.com/support/processors/sb/cs-009861.htm

Signed-off-by: Yong Wang <yong.y.wang@intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <20090610090612.GA26580@ywang-moblin2.bj.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/kernel/cpu/perf_counter.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 40978aa..a49a82c 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -1407,7 +1407,8 @@ static int intel_pmu_init(void)
 	 * Install the hw-cache-events table:
 	 */
 	switch (boot_cpu_data.x86_model) {
-	case 17:
+	case 15:
+	case 23:
 		memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 

Re: [PATCH -tip] perf_counter/x86: Fix the model number of Intel Core2 processors

[Arnd Bergmann]

On Wednesday 10 June 2009, Yong Wang wrote:
> diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
> index 40978aa..a49a82c 100644
> --- a/arch/x86/kernel/cpu/perf_counter.c
> +++ b/arch/x86/kernel/cpu/perf_counter.c
> @@ -1407,7 +1407,8 @@ static int intel_pmu_init(void)
>          * Install the hw-cache-events table:
>          */
>         switch (boot_cpu_data.x86_model) {
> -       case 17:
> +       case 15:
> +       case 23:
>                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
>                        sizeof(hw_cache_event_ids));

There are actually four model numbers that refer to the same
core microarchitecture:

model 15: original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe"
model 22: single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L"
model 23: current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale"
model 29: six-core 45 nm xeon "Dunnington"

You should probably list all of them here.

	Arnd <><

Re: [PATCH -tip] perf_counter/x86: Fix the model number of Intel Core2 processors

[Ingo Molnar]

* Arnd Bergmann <arnd@arndb.de> wrote:

> On Wednesday 10 June 2009, Yong Wang wrote:
> > diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
> > index 40978aa..a49a82c 100644
> > --- a/arch/x86/kernel/cpu/perf_counter.c
> > +++ b/arch/x86/kernel/cpu/perf_counter.c
> > @@ -1407,7 +1407,8 @@ static int intel_pmu_init(void)
> >          * Install the hw-cache-events table:
> >          */
> >         switch (boot_cpu_data.x86_model) {
> > -       case 17:
> > +       case 15:
> > +       case 23:
> >                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
> >                        sizeof(hw_cache_event_ids));
> 
> There are actually four model numbers that refer to the same
> core microarchitecture:
> 
> model 15: original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe"
> model 22: single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L"
> model 23: current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale"
> model 29: six-core 45 nm xeon "Dunnington"
> 
> You should probably list all of them here.

Yeah - i've amended the commit with your suggestions - thanks Arnd!

	Ingo

[tip:perfcounters/core] perf_counter/x86: Fix the model number of Intel Core2 processors

[tip-bot for Yong Wang]

Commit-ID:  dc81081b2d9a6a9d64dad1bef1e5fc9fb660e53e
Gitweb:     http://git.kernel.org/tip/dc81081b2d9a6a9d64dad1bef1e5fc9fb660e53e
Author:     Yong Wang <yong.y.wang@linux.intel.com>
AuthorDate: Wed, 10 Jun 2009 17:06:12 +0800
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Wed, 10 Jun 2009 13:04:43 +0200

perf_counter/x86: Fix the model number of Intel Core2 processors

Fix the model number of Intel Core2 processors according to the
documentation: Intel Processor Identification with the CPUID
Instruction: http://www.intel.com/support/processors/sb/cs-009861.htm

Signed-off-by: Yong Wang <yong.y.wang@intel.com>
Also-Reported-by: Arnd Bergmann <arnd@arndb.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <20090610090612.GA26580@ywang-moblin2.bj.intel.com>
[ Added two more model numbers suggested by Arnd Bergmann ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/kernel/cpu/perf_counter.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 40978aa..49f2585 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -1407,7 +1407,10 @@ static int intel_pmu_init(void)
 	 * Install the hw-cache-events table:
 	 */
 	switch (boot_cpu_data.x86_model) {
-	case 17:
+	case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
+	case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
+	case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
+	case 29: /* six-core 45 nm xeon "Dunnington" */
 		memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));