From: Yong Wang <yong.y.wang@linux.intel.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org,
Arjan van de Ven <arjan@infradead.org>
Subject: Re: [PATCH -tip] perf_counter/x86: Correct some event and umask values for Intel processors
Date: Thu, 11 Jun 2009 16:27:10 +0800 [thread overview]
Message-ID: <20090611082710.GA29784@ywang-moblin2.bj.intel.com> (raw)
In-Reply-To: <20090610104242.GB27724@elte.hu>
> > Btw, one thing I don't quite understand is why you aliased
> > dtlb-write-ops to l1d-write-ops when setting event and umask
> > values. Are they the same event?
>
> No, they are indeed different events - that's a bug in the table,
> good spotting. Mind sending a (tested) patch for it?
>
I'm a little confused. By dtlb-write-ops, do you want to count the
number of times that DTLB is accessed due to store operations or the
number of times that DTLB entries are written to, i.e. updated?
Btw, do you know whether virtual cache is employed or not on
atom/core2/nehalem so that tlb won't be accessed when accessing l1
caches?
-Yong
next prev parent reply other threads:[~2009-06-11 8:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-09 13:15 [PATCH -tip] perf_counter/x86: Correct some event and umask values for Intel processors Yong Wang
2009-06-09 14:16 ` Ingo Molnar
2009-06-10 5:36 ` Yong Wang
2009-06-10 10:42 ` Ingo Molnar
2009-06-11 8:27 ` Yong Wang [this message]
2009-06-11 11:26 ` Ingo Molnar
2009-06-12 8:15 ` Yong Wang
2009-06-09 14:52 ` [tip:perfcounters/core] perf_counter, x86: " tip-bot for Yong Wang
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