[PATCH -tip] x86: perf_counter fix L1-data-Cache-Store-Referencees for AMD

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* [PATCH -tip] x86: perf_counter fix L1-data-Cache-Store-Referencees for AMD
@ 2009-06-18 13:28 Jaswinder Singh Rajput
  2009-06-20  7:49 ` [PATCH -tip RESEND] " Jaswinder Singh Rajput
  0 siblings, 1 reply; 5+ messages in thread
From: Jaswinder Singh Rajput @ 2009-06-18 13:28 UTC (permalink / raw)
  To: Ingo Molnar, Thomas Gleixner, x86 maintainers, LKML


Fix AMD event for Data Cache Refills from System.

By this patch :

./tools/perf/perf stat -e l1d -e l1d-misses -e l1d-write -e l1d-prefetch -e l1d-prefetch-miss -e l1i -e l1i-misses -e l1i-prefetch -e l2 -e l2-misses -e l2-write -e dtlb -e dtlb-misses -e itlb -e itlb-misses -e bpu -e bpu-misses ls /dev/ > /dev/null

 Performance counter stats for 'ls /dev/':

        2499484  L1-data-Cache-Load-Referencees  (scaled from 3.97%)
          70347  L1-data-Cache-Load-Misses  (scaled from 7.30%)
           9360  L1-data-Cache-Store-Referencees  (scaled from 8.64%)
          32804  L1-data-Cache-Prefetch-Referencees  (scaled from 17.72%)
           7693  L1-data-Cache-Prefetch-Misses  (scaled from 22.97%)
        2180945  L1-instruction-Cache-Load-Referencees  (scaled from 28.48%)
          14518  L1-instruction-Cache-Load-Misses  (scaled from 35.00%)
           2405  L1-instruction-Cache-Prefetch-Referencees  (scaled from 34.89%)
          71387  L2-Cache-Load-Referencees  (scaled from 34.94%)
          18732  L2-Cache-Load-Misses  (scaled from 34.92%)
          79918  L2-Cache-Store-Referencees  (scaled from 36.02%)
        1295294  Data-TLB-Cache-Load-Referencees  (scaled from 35.99%)
          30896  Data-TLB-Cache-Load-Misses  (scaled from 33.36%)
        1222030  Instruction-TLB-Cache-Load-Referencees  (scaled from 29.46%)
            357  Instruction-TLB-Cache-Load-Misses  (scaled from 20.46%)
         530888  Branch-Cache-Load-Referencees  (scaled from 11.48%)
           8638  Branch-Cache-Load-Misses  (scaled from 5.09%)

    0.011295149  seconds time elapsed.

Earlier it always shows value 0.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/perf_counter.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index ce1ae3f..37facc5 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -401,7 +401,7 @@ static const u64 amd_hw_cache_event_ids
 		[ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
 	},
 	[ C(OP_WRITE) ] = {
-		[ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */
+		[ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
 		[ C(RESULT_MISS)   ] = 0,
 	},
 	[ C(OP_PREFETCH) ] = {
-- 
1.6.0.6




^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH -tip RESEND] x86: perf_counter fix L1-data-Cache-Store-Referencees for AMD
  2009-06-18 13:28 [PATCH -tip] x86: perf_counter fix L1-data-Cache-Store-Referencees for AMD Jaswinder Singh Rajput
@ 2009-06-20  7:49 ` Jaswinder Singh Rajput
  2009-06-20 17:43   ` Ingo Molnar
                     ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Jaswinder Singh Rajput @ 2009-06-20  7:49 UTC (permalink / raw)
  To: Ingo Molnar; +Cc: Thomas Gleixner, x86 maintainers, LKML


Fix AMD's Data Cache Refills from System event.

By this patch :

./tools/perf/perf stat -e l1d -e l1d-misses -e l1d-write -e l1d-prefetch -e l1d-prefetch-miss -e l1i -e l1i-misses -e l1i-prefetch -e l2 -e l2-misses -e l2-write -e dtlb -e dtlb-misses -e itlb -e itlb-misses -e bpu -e bpu-misses ls /dev/ > /dev/null

 Performance counter stats for 'ls /dev/':

        2499484  L1-data-Cache-Load-Referencees  (scaled from 3.97%)
          70347  L1-data-Cache-Load-Misses  (scaled from 7.30%)
           9360  L1-data-Cache-Store-Referencees  (scaled from 8.64%)
          32804  L1-data-Cache-Prefetch-Referencees  (scaled from 17.72%)
           7693  L1-data-Cache-Prefetch-Misses  (scaled from 22.97%)
        2180945  L1-instruction-Cache-Load-Referencees  (scaled from 28.48%)
          14518  L1-instruction-Cache-Load-Misses  (scaled from 35.00%)
           2405  L1-instruction-Cache-Prefetch-Referencees  (scaled from 34.89%)
          71387  L2-Cache-Load-Referencees  (scaled from 34.94%)
          18732  L2-Cache-Load-Misses  (scaled from 34.92%)
          79918  L2-Cache-Store-Referencees  (scaled from 36.02%)
        1295294  Data-TLB-Cache-Load-Referencees  (scaled from 35.99%)
          30896  Data-TLB-Cache-Load-Misses  (scaled from 33.36%)
        1222030  Instruction-TLB-Cache-Load-Referencees  (scaled from 29.46%)
            357  Instruction-TLB-Cache-Load-Misses  (scaled from 20.46%)
         530888  Branch-Cache-Load-Referencees  (scaled from 11.48%)
           8638  Branch-Cache-Load-Misses  (scaled from 5.09%)

    0.011295149  seconds time elapsed.

Earlier it always shows value 0.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
---
 arch/x86/kernel/cpu/perf_counter.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index ce1ae3f..37facc5 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -401,7 +401,7 @@ static const u64 amd_hw_cache_event_ids
 		[ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
 	},
 	[ C(OP_WRITE) ] = {
-		[ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */
+		[ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
 		[ C(RESULT_MISS)   ] = 0,
 	},
 	[ C(OP_PREFETCH) ] = {
-- 
1.6.0.6




^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH -tip RESEND] x86: perf_counter fix L1-data-Cache-Store-Referencees for AMD
  2009-06-20  7:49 ` [PATCH -tip RESEND] " Jaswinder Singh Rajput
@ 2009-06-20 17:43   ` Ingo Molnar
  2009-06-20 17:45   ` [tip:perfcounters/urgent] perf_counter, x8: Fix " tip-bot for Jaswinder Singh Rajput
  2009-06-21 11:27   ` tip-bot for Jaswinder Singh Rajput
  2 siblings, 0 replies; 5+ messages in thread
From: Ingo Molnar @ 2009-06-20 17:43 UTC (permalink / raw)
  To: Jaswinder Singh Rajput; +Cc: Thomas Gleixner, x86 maintainers, LKML


* Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:

> Fix AMD's Data Cache Refills from System event.
> 
> By this patch :
> 
> ./tools/perf/perf stat -e l1d -e l1d-misses -e l1d-write -e l1d-prefetch -e l1d-prefetch-miss -e l1i -e l1i-misses -e l1i-prefetch -e l2 -e l2-misses -e l2-write -e dtlb -e dtlb-misses -e itlb -e itlb-misses -e bpu -e bpu-misses ls /dev/ > /dev/null
> 
>  Performance counter stats for 'ls /dev/':
> 
>         2499484  L1-data-Cache-Load-Referencees  (scaled from 3.97%)
>           70347  L1-data-Cache-Load-Misses  (scaled from 7.30%)
>            9360  L1-data-Cache-Store-Referencees  (scaled from 8.64%)
>           32804  L1-data-Cache-Prefetch-Referencees  (scaled from 17.72%)
>            7693  L1-data-Cache-Prefetch-Misses  (scaled from 22.97%)
>         2180945  L1-instruction-Cache-Load-Referencees  (scaled from 28.48%)
>           14518  L1-instruction-Cache-Load-Misses  (scaled from 35.00%)
>            2405  L1-instruction-Cache-Prefetch-Referencees  (scaled from 34.89%)
>           71387  L2-Cache-Load-Referencees  (scaled from 34.94%)
>           18732  L2-Cache-Load-Misses  (scaled from 34.92%)
>           79918  L2-Cache-Store-Referencees  (scaled from 36.02%)
>         1295294  Data-TLB-Cache-Load-Referencees  (scaled from 35.99%)
>           30896  Data-TLB-Cache-Load-Misses  (scaled from 33.36%)
>         1222030  Instruction-TLB-Cache-Load-Referencees  (scaled from 29.46%)
>             357  Instruction-TLB-Cache-Load-Misses  (scaled from 20.46%)
>          530888  Branch-Cache-Load-Referencees  (scaled from 11.48%)
>            8638  Branch-Cache-Load-Misses  (scaled from 5.09%)
> 
>     0.011295149  seconds time elapsed.
> 
> Earlier it always shows value 0.
> 
> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> ---
>  arch/x86/kernel/cpu/perf_counter.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
> index ce1ae3f..37facc5 100644
> --- a/arch/x86/kernel/cpu/perf_counter.c
> +++ b/arch/x86/kernel/cpu/perf_counter.c
> @@ -401,7 +401,7 @@ static const u64 amd_hw_cache_event_ids
>  		[ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
>  	},
>  	[ C(OP_WRITE) ] = {
> -		[ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */
> +		[ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
>  		[ C(RESULT_MISS)   ] = 0,
>  	},
>  	[ C(OP_PREFETCH) ] = {

Applied to tip:perfcounters/urgent, thanks Jaswinder!

	Ingo

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [tip:perfcounters/urgent] perf_counter, x8: Fix L1-data-Cache-Store-Referencees for AMD
  2009-06-20  7:49 ` [PATCH -tip RESEND] " Jaswinder Singh Rajput
  2009-06-20 17:43   ` Ingo Molnar
@ 2009-06-20 17:45   ` tip-bot for Jaswinder Singh Rajput
  2009-06-21 11:27   ` tip-bot for Jaswinder Singh Rajput
  2 siblings, 0 replies; 5+ messages in thread
From: tip-bot for Jaswinder Singh Rajput @ 2009-06-20 17:45 UTC (permalink / raw)
  To: linux-tip-commits
  Cc: linux-kernel, hpa, mingo, jaswinder, tglx, mingo, jaswinderrajput

Commit-ID:  baed11e65b6e4e191199846c78fd33aae5ce30f5
Gitweb:     http://git.kernel.org/tip/baed11e65b6e4e191199846c78fd33aae5ce30f5
Author:     Jaswinder Singh Rajput <jaswinder@kernel.org>
AuthorDate: Sat, 20 Jun 2009 13:19:25 +0530
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Sat, 20 Jun 2009 19:42:48 +0200

perf_counter, x8: Fix L1-data-Cache-Store-Referencees for AMD

Fix AMD's Data Cache Refills from System event.

After this patch :

 ./tools/perf/perf stat -e l1d -e l1d-misses -e l1d-write -e l1d-prefetch -e l1d-prefetch-miss -e l1i -e l1i-misses -e l1i-prefetch -e l2 -e l2-misses -e l2-write -e dtlb -e dtlb-misses -e itlb -e itlb-misses -e bpu -e bpu-misses ls /dev/ > /dev/null

 Performance counter stats for 'ls /dev/':

        2499484  L1-data-Cache-Load-Referencees             (scaled from 3.97%)
          70347  L1-data-Cache-Load-Misses                  (scaled from 7.30%)
           9360  L1-data-Cache-Store-Referencees            (scaled from 8.64%)
          32804  L1-data-Cache-Prefetch-Referencees         (scaled from 17.72%)
           7693  L1-data-Cache-Prefetch-Misses              (scaled from 22.97%)
        2180945  L1-instruction-Cache-Load-Referencees      (scaled from 28.48%)
          14518  L1-instruction-Cache-Load-Misses           (scaled from 35.00%)
           2405  L1-instruction-Cache-Prefetch-Referencees  (scaled from 34.89%)
          71387  L2-Cache-Load-Referencees                  (scaled from 34.94%)
          18732  L2-Cache-Load-Misses                       (scaled from 34.92%)
          79918  L2-Cache-Store-Referencees                 (scaled from 36.02%)
        1295294  Data-TLB-Cache-Load-Referencees            (scaled from 35.99%)
          30896  Data-TLB-Cache-Load-Misses                 (scaled from 33.36%)
        1222030  Instruction-TLB-Cache-Load-Referencees     (scaled from 29.46%)
            357  Instruction-TLB-Cache-Load-Misses          (scaled from 20.46%)
         530888  Branch-Cache-Load-Referencees              (scaled from 11.48%)
           8638  Branch-Cache-Load-Misses                   (scaled from 5.09%)

    0.011295149  seconds time elapsed.

Earlier it always shows value 0.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
LKML-Reference: <1245484165.3102.6.camel@localhost.localdomain>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/kernel/cpu/perf_counter.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 76dfef2..22eb3a1 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -401,7 +401,7 @@ static const u64 amd_hw_cache_event_ids
 		[ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
 	},
 	[ C(OP_WRITE) ] = {
-		[ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */
+		[ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
 		[ C(RESULT_MISS)   ] = 0,
 	},
 	[ C(OP_PREFETCH) ] = {

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [tip:perfcounters/urgent] perf_counter, x8: Fix L1-data-Cache-Store-Referencees for AMD
  2009-06-20  7:49 ` [PATCH -tip RESEND] " Jaswinder Singh Rajput
  2009-06-20 17:43   ` Ingo Molnar
  2009-06-20 17:45   ` [tip:perfcounters/urgent] perf_counter, x8: Fix " tip-bot for Jaswinder Singh Rajput
@ 2009-06-21 11:27   ` tip-bot for Jaswinder Singh Rajput
  2 siblings, 0 replies; 5+ messages in thread
From: tip-bot for Jaswinder Singh Rajput @ 2009-06-21 11:27 UTC (permalink / raw)
  To: linux-tip-commits
  Cc: linux-kernel, hpa, mingo, jaswinder, tglx, mingo, jaswinderrajput

Commit-ID:  d9f2a5ecb2846d0fd368fb4c45182e43f38e4471
Gitweb:     http://git.kernel.org/tip/d9f2a5ecb2846d0fd368fb4c45182e43f38e4471
Author:     Jaswinder Singh Rajput <jaswinder@kernel.org>
AuthorDate: Sat, 20 Jun 2009 13:19:25 +0530
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Sun, 21 Jun 2009 13:25:55 +0200

perf_counter, x8: Fix L1-data-Cache-Store-Referencees for AMD

Fix AMD's Data Cache Refills from System event.

After this patch :

 ./tools/perf/perf stat -e l1d -e l1d-misses -e l1d-write -e l1d-prefetch -e l1d-prefetch-miss -e l1i -e l1i-misses -e l1i-prefetch -e l2 -e l2-misses -e l2-write -e dtlb -e dtlb-misses -e itlb -e itlb-misses -e bpu -e bpu-misses ls /dev/ > /dev/null

 Performance counter stats for 'ls /dev/':

        2499484  L1-data-Cache-Load-Referencees             (scaled from 3.97%)
          70347  L1-data-Cache-Load-Misses                  (scaled from 7.30%)
           9360  L1-data-Cache-Store-Referencees            (scaled from 8.64%)
          32804  L1-data-Cache-Prefetch-Referencees         (scaled from 17.72%)
           7693  L1-data-Cache-Prefetch-Misses              (scaled from 22.97%)
        2180945  L1-instruction-Cache-Load-Referencees      (scaled from 28.48%)
          14518  L1-instruction-Cache-Load-Misses           (scaled from 35.00%)
           2405  L1-instruction-Cache-Prefetch-Referencees  (scaled from 34.89%)
          71387  L2-Cache-Load-Referencees                  (scaled from 34.94%)
          18732  L2-Cache-Load-Misses                       (scaled from 34.92%)
          79918  L2-Cache-Store-Referencees                 (scaled from 36.02%)
        1295294  Data-TLB-Cache-Load-Referencees            (scaled from 35.99%)
          30896  Data-TLB-Cache-Load-Misses                 (scaled from 33.36%)
        1222030  Instruction-TLB-Cache-Load-Referencees     (scaled from 29.46%)
            357  Instruction-TLB-Cache-Load-Misses          (scaled from 20.46%)
         530888  Branch-Cache-Load-Referencees              (scaled from 11.48%)
           8638  Branch-Cache-Load-Misses                   (scaled from 5.09%)

    0.011295149  seconds time elapsed.

Earlier it always shows value 0.

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
LKML-Reference: <1245484165.3102.6.camel@localhost.localdomain>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/kernel/cpu/perf_counter.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 76dfef2..22eb3a1 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -401,7 +401,7 @@ static const u64 amd_hw_cache_event_ids
 		[ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
 	},
 	[ C(OP_WRITE) ] = {
-		[ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */
+		[ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
 		[ C(RESULT_MISS)   ] = 0,
 	},
 	[ C(OP_PREFETCH) ] = {

^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2009-06-21 11:28 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-06-18 13:28 [PATCH -tip] x86: perf_counter fix L1-data-Cache-Store-Referencees for AMD Jaswinder Singh Rajput
2009-06-20  7:49 ` [PATCH -tip RESEND] " Jaswinder Singh Rajput
2009-06-20 17:43   ` Ingo Molnar
2009-06-20 17:45   ` [tip:perfcounters/urgent] perf_counter, x8: Fix " tip-bot for Jaswinder Singh Rajput
2009-06-21 11:27   ` tip-bot for Jaswinder Singh Rajput

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