Re: [PATCH 2/2 -tip] perf_counter: parse-events.c introduce alias member in event_symbol

[Ingo Molnar <mingo@elte.hu>]

* Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:

> On Mon, 2009-06-22 at 16:10 +0200, Ingo Molnar wrote:
> > yeah, somethig like that. I'd suggest to print out the actual 
> > measured events:
> > 
> >     cache-references      10123 events
> >     cache-misses             15 events
> > 
> > and if something does not appear to be ticking then do something 
> > like:
> > 
> >     cache-misses          <inactive>
> > 
> > I.e. 'perf test' could be a quick way both to users and to 
> > developers to see all possible hw and sw events.
> > 
> > Perhaps builtin-test.c should also do specific testcases for certain 
> > counters - say intentionally migrate to a CPU and back to see the 
> > CPU-migration count.
> > 
> > Also, you seem to have copied builtin-stat.c, right? Try to 
> > librarize as much of the functionality (into util/*) to make the 
> > resulting linecount increase as small as possible.
> 
> perf test also need some command to execute otherwise it will also 
> show long list of <inactive>

I think what it should do is to execute test-cases _internally_. Not 
just execute some random command on the system and hope for events.

> I think better I should support all events in perf stat so user 
> can get better information from it and we can all add some other 
> testing option to it.

I agree - see my previous mail about how to achieve this better: we 
should extend event string parsing with wildcards (regex) and with 
'set of events' symbols that act as convenient specifiers for 
certain typical uses.

> Anyway currently it looks like this :
> 
> [RFC][PATCH] perf_counter tools: introduce perf test to test event for ticks
> 
> perf test to Test performance counter events, its output on AMD box :
> 
> ./perf test -a -- ls -lR > /dev/null
> 
>  Performance counter stats for 'ls' -lR:
> 
>  cycles                                             1226819954
>  instructions                                        283680441
>  cache-references                                    144893559
>  cache-misses                                          3268438
>  branches                                             37488241
>  branch-misses                                         2464027
>  bus-cycles                                         <inactive>
>  cpu-clock-msecs                                   17175506056
>  task-clock-msecs                                  17175086665
>  page-faults                                               488
>  minor-faults                                              488
>  major-faults                                       <inactive>

We should try to provoke a real major fault (i.e. a fault with IO) 
here. Not sure how though :-)

>  context-switches                                         7956
>  CPU-migrations                                              7

this needs to be provoked intentionally via sched_setaffinity(): 
first migrate to cpu0, then to cpu1.

>  L1-data-Cache-Load-Referencees                      398303881
>  L1-data-Cache-Load-Misses                             3552374
>  L1-data-Cache-Store-Referencees                        270178
>  L1-data-Cache-Store-Misses                         <inactive>

this is probably inactive due to AMD not having events for that and 
the generic cache event being 0 there, right?

>  L1-data-Cache-Prefetch-Referencees                     611622
>  L1-data-Cache-Prefetch-Misses                          399730
>  L1-instruction-Cache-Load-Referencees               124696447
>  L1-instruction-Cache-Load-Misses                      2912802
>  L1-instruction-Cache-Store-Referencees             <inactive>
>  L1-instruction-Cache-Store-Misses                  <inactive>
>  L1-instruction-Cache-Prefetch-Referencees              156576
>  L1-instruction-Cache-Prefetch-Misses               <inactive>
>  L2-Cache-Load-Referencees                             4312353
>  L2-Cache-Load-Misses                                   470382
>  L2-Cache-Store-Referencees                            4392945
>  L2-Cache-Store-Misses                              <inactive>
>  L2-Cache-Prefetch-Referencees                      <inactive>
>  L2-Cache-Prefetch-Misses                           <inactive>
>  Data-TLB-Cache-Load-Referencees                     127076487
>  Data-TLB-Cache-Load-Misses                            1930048
>  Data-TLB-Cache-Store-Referencees                   <inactive>
>  Data-TLB-Cache-Store-Misses                        <inactive>
>  Data-TLB-Cache-Prefetch-Referencees                <inactive>
>  Data-TLB-Cache-Prefetch-Misses                     <inactive>
>  Instruction-TLB-Cache-Load-Referencees              132768077
>  Instruction-TLB-Cache-Load-Misses                        6406
>  Instruction-TLB-Cache-Store-Referencees            <inactive>
>  Instruction-TLB-Cache-Store-Misses                 <inactive>
>  Instruction-TLB-Cache-Prefetch-Referencees         <inactive>
>  Instruction-TLB-Cache-Prefetch-Misses              <inactive>
>  Branch-Cache-Load-Referencees                        58030210
>  Branch-Cache-Load-Misses                              3257804
>  Branch-Cache-Store-Referencees                     <inactive>
>  Branch-Cache-Store-Misses                          <inactive>
>  Branch-Cache-Prefetch-Referencees                  <inactive>
>  Branch-Cache-Prefetch-Misses                       <inactive>
> 
>     8.681671511  seconds time elapsed.

looks nice.

	Ingo