From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754192AbZHGQuA (ORCPT ); Fri, 7 Aug 2009 12:50:00 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754091AbZHGQuA (ORCPT ); Fri, 7 Aug 2009 12:50:00 -0400 Received: from ru.mvista.com ([213.79.90.228]:1763 "EHLO buildserver.ru.mvista.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752750AbZHGQt7 (ORCPT ); Fri, 7 Aug 2009 12:49:59 -0400 Date: Fri, 7 Aug 2009 20:49:57 +0400 From: Anton Vorontsov To: Andrew Morton Cc: Pierre Ossman , Kumar Gala , Ben Dooks , Sascha Hauer , linux-kernel@vger.kernel.org, sdhci-devel@lists.ossman.eu, linuxppc-dev@ozlabs.org Subject: [PATCH 2/4] sdhci-of: Avoid writing reserved bits into host control register Message-ID: <20090807164957.GA524@oksana.dev.rtsoft.ru> References: <20090807163940.GA29192@oksana.dev.rtsoft.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20090807163940.GA29192@oksana.dev.rtsoft.ru> User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SDHCI core tries to write HISPD bit into the host control register, but the eSDHC controllers don't have that bit, and that causes all sorts of misbehaviour when using 4-bit mode capable SD cards. Signed-off-by: Anton Vorontsov --- drivers/mmc/host/sdhci-of.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c index 92b5667..8440fd9 100644 --- a/drivers/mmc/host/sdhci-of.c +++ b/drivers/mmc/host/sdhci-of.c @@ -48,6 +48,8 @@ struct sdhci_of_host { #define ESDHC_CLOCK_HCKEN 0x00000002 #define ESDHC_CLOCK_IPGEN 0x00000001 +#define ESDHC_HOST_CONTROL_RES 0x05 + static u32 esdhc_readl(struct sdhci_host *host, int reg) { return in_be32(host->ioaddr + reg); @@ -109,6 +111,10 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg) int base = reg & ~0x3; int shift = (reg & 0x3) * 8; + /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */ + if (reg == SDHCI_HOST_CONTROL) + val &= ~ESDHC_HOST_CONTROL_RES; + clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); } -- 1.6.3.3