* [patch 1/3] x86, perf_counter, bts: fail if BTS is not available
2009-09-02 14:04 [patch 0/3] x86, perf_counter, bts: incorporate review feedback and fix bugs markus.t.metzger
@ 2009-09-02 14:04 ` markus.t.metzger
2009-09-04 7:58 ` [tip:perfcounters/core] x86, perf_counter, bts: Fail " tip-bot for markus.t.metzger@intel.com
2009-09-02 14:04 ` [patch 2/3] x86, perf_counter, bts: correct pointer-to-u64 casts markus.t.metzger
2009-09-02 14:04 ` [patch 3/3] x86, perf_counter, bts: do not allow kernel BTS tracing markus.t.metzger
2 siblings, 1 reply; 7+ messages in thread
From: markus.t.metzger @ 2009-09-02 14:04 UTC (permalink / raw)
To: mingo, tglx, hpa
Cc: markus.t.metzger, a.p.zijlstra, linux-kernel, Markus Metzger
[-- Attachment #1: tip.master.perf_counter.fail_when_not_available.patch --]
[-- Type: text/plain, Size: 1855 bytes --]
Reserve PERF_COUNT_HW_BRANCH_INSTRUCTIONS with sample_period == 1
for BTS tracing and fail, if BTS is not available.
CC: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
---
arch/x86/kernel/cpu/perf_counter.c | 25 11 + 14 - 0 !
1 files changed, 11 insertions(+), 14 deletions(-)
Index: b/arch/x86/kernel/cpu/perf_counter.c
===================================================================
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -769,7 +769,7 @@ static int reserve_bts_hardware(void)
int cpu, err = 0;
if (!bts_available())
- return -EOPNOTSUPP;
+ return 0;
get_online_cpus();
@@ -914,7 +914,7 @@ static int __hw_perf_counter_init(struct
if (!reserve_pmc_hardware())
err = -EBUSY;
else
- reserve_bts_hardware();
+ err = reserve_bts_hardware();
}
if (!err)
atomic_inc(&active_counters);
@@ -979,6 +979,13 @@ static int __hw_perf_counter_init(struct
if (config == -1LL)
return -EINVAL;
+ /*
+ * Branch tracing:
+ */
+ if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
+ (hwc->sample_period == 1) && !bts_available())
+ return -EOPNOTSUPP;
+
hwc->config |= config;
return 0;
@@ -1355,19 +1362,9 @@ static int x86_pmu_enable(struct perf_co
idx = fixed_mode_idx(counter, hwc);
if (idx == X86_PMC_IDX_FIXED_BTS) {
- /*
- * Try to use BTS for branch tracing. If that is not
- * available, try to get a generic counter.
- */
- if (unlikely(!cpuc->ds))
- goto try_generic;
-
- /*
- * Try to get the fixed counter, if that is already taken
- * then try to get a generic counter:
- */
+ /* BTS is already occupied. */
if (test_and_set_bit(idx, cpuc->used_mask))
- goto try_generic;
+ return -EAGAIN;
hwc->config_base = 0;
hwc->counter_base = 0;
--
[-- Attachment #2: Type: text/plain, Size: 656 bytes --]
---------------------------------------------------------------------
Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/Muenchen Germany
Sitz der Gesellschaft: Feldkirchen bei Muenchen
Geschaeftsfuehrer: Douglas Lusk, Peter Gleissner, Hannes Schwaderer
Registergericht: Muenchen HRB 47456 Ust.-IdNr.
VAT Registration No.: DE129385895
Citibank Frankfurt (BLZ 502 109 00) 600119052
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
^ permalink raw reply [flat|nested] 7+ messages in thread* [tip:perfcounters/core] x86, perf_counter, bts: Fail if BTS is not available
2009-09-02 14:04 ` [patch 1/3] x86, perf_counter, bts: fail if BTS is not available markus.t.metzger
@ 2009-09-04 7:58 ` tip-bot for markus.t.metzger@intel.com
0 siblings, 0 replies; 7+ messages in thread
From: tip-bot for markus.t.metzger@intel.com @ 2009-09-04 7:58 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, a.p.zijlstra, markus.t.metzger, tglx,
mingo
Commit-ID: 747b50aaf728987732e6ff3ba10aba4acc4e0277
Gitweb: http://git.kernel.org/tip/747b50aaf728987732e6ff3ba10aba4acc4e0277
Author: markus.t.metzger@intel.com <markus.t.metzger@intel.com>
AuthorDate: Wed, 2 Sep 2009 16:04:46 +0200
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 4 Sep 2009 09:26:39 +0200
x86, perf_counter, bts: Fail if BTS is not available
Reserve PERF_COUNT_HW_BRANCH_INSTRUCTIONS with sample_period ==
1 for BTS tracing and fail, if BTS is not available.
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <20090902140612.943801000@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/cpu/perf_counter.c | 25 +++++++++++--------------
1 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 396e35d..2f41874 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -769,7 +769,7 @@ static int reserve_bts_hardware(void)
int cpu, err = 0;
if (!bts_available())
- return -EOPNOTSUPP;
+ return 0;
get_online_cpus();
@@ -914,7 +914,7 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
if (!reserve_pmc_hardware())
err = -EBUSY;
else
- reserve_bts_hardware();
+ err = reserve_bts_hardware();
}
if (!err)
atomic_inc(&active_counters);
@@ -979,6 +979,13 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
if (config == -1LL)
return -EINVAL;
+ /*
+ * Branch tracing:
+ */
+ if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
+ (hwc->sample_period == 1) && !bts_available())
+ return -EOPNOTSUPP;
+
hwc->config |= config;
return 0;
@@ -1355,19 +1362,9 @@ static int x86_pmu_enable(struct perf_counter *counter)
idx = fixed_mode_idx(counter, hwc);
if (idx == X86_PMC_IDX_FIXED_BTS) {
- /*
- * Try to use BTS for branch tracing. If that is not
- * available, try to get a generic counter.
- */
- if (unlikely(!cpuc->ds))
- goto try_generic;
-
- /*
- * Try to get the fixed counter, if that is already taken
- * then try to get a generic counter:
- */
+ /* BTS is already occupied. */
if (test_and_set_bit(idx, cpuc->used_mask))
- goto try_generic;
+ return -EAGAIN;
hwc->config_base = 0;
hwc->counter_base = 0;
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [patch 2/3] x86, perf_counter, bts: correct pointer-to-u64 casts
2009-09-02 14:04 [patch 0/3] x86, perf_counter, bts: incorporate review feedback and fix bugs markus.t.metzger
2009-09-02 14:04 ` [patch 1/3] x86, perf_counter, bts: fail if BTS is not available markus.t.metzger
@ 2009-09-02 14:04 ` markus.t.metzger
2009-09-04 7:58 ` [tip:perfcounters/core] x86, perf_counter, bts: Correct " tip-bot for markus.t.metzger@intel.com
2009-09-02 14:04 ` [patch 3/3] x86, perf_counter, bts: do not allow kernel BTS tracing markus.t.metzger
2 siblings, 1 reply; 7+ messages in thread
From: markus.t.metzger @ 2009-09-02 14:04 UTC (permalink / raw)
To: mingo, tglx, hpa
Cc: markus.t.metzger, a.p.zijlstra, linux-kernel, Markus Metzger
[-- Attachment #1: tip.master.perf_counter.correct_pointer_to_u64_casts.patch --]
[-- Type: text/plain, Size: 2296 bytes --]
On 32bit, pointers in the DS AREA configuration are cast to u64. The
current (long) cast to avoid compiler warnings results in a signed
64bit address.
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
---
arch/x86/kernel/cpu/perf_counter.c | 24 12 + 12 - 0 !
1 files changed, 12 insertions(+), 12 deletions(-)
Index: b/arch/x86/kernel/cpu/perf_counter.c
===================================================================
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -726,7 +726,8 @@ static inline void init_debug_store_on_c
return;
wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
- (u32)((u64)(long)ds), (u32)((u64)(long)ds >> 32));
+ (u32)((u64)(unsigned long)ds),
+ (u32)((u64)(unsigned long)ds >> 32));
}
static inline void fini_debug_store_on_cpu(int cpu)
@@ -757,7 +758,7 @@ static void release_bts_hardware(void)
per_cpu(cpu_hw_counters, cpu).ds = NULL;
- kfree((void *)(long)ds->bts_buffer_base);
+ kfree((void *)(unsigned long)ds->bts_buffer_base);
kfree(ds);
}
@@ -788,7 +789,7 @@ static int reserve_bts_hardware(void)
break;
}
- ds->bts_buffer_base = (u64)(long)buffer;
+ ds->bts_buffer_base = (u64)(unsigned long)buffer;
ds->bts_index = ds->bts_buffer_base;
ds->bts_absolute_maximum =
ds->bts_buffer_base + BTS_BUFFER_SIZE;
@@ -1491,7 +1492,7 @@ static void intel_pmu_drain_bts_buffer(s
};
struct perf_counter *counter = cpuc->counters[X86_PMC_IDX_FIXED_BTS];
unsigned long orig_ip = data->regs->ip;
- u64 at;
+ struct bts_record *at, *top;
if (!counter)
return;
@@ -1499,19 +1500,18 @@ static void intel_pmu_drain_bts_buffer(s
if (!ds)
return;
- for (at = ds->bts_buffer_base;
- at < ds->bts_index;
- at += sizeof(struct bts_record)) {
- struct bts_record *rec = (struct bts_record *)(long)at;
+ at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
+ top = (struct bts_record *)(unsigned long)ds->bts_index;
- data->regs->ip = rec->from;
- data->addr = rec->to;
+ ds->bts_index = ds->bts_buffer_base;
+
+ for (; at < top; at++) {
+ data->regs->ip = at->from;
+ data->addr = at->to;
perf_counter_output(counter, 1, data);
}
- ds->bts_index = ds->bts_buffer_base;
-
data->regs->ip = orig_ip;
data->addr = 0;
--
[-- Attachment #2: Type: text/plain, Size: 656 bytes --]
---------------------------------------------------------------------
Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/Muenchen Germany
Sitz der Gesellschaft: Feldkirchen bei Muenchen
Geschaeftsfuehrer: Douglas Lusk, Peter Gleissner, Hannes Schwaderer
Registergericht: Muenchen HRB 47456 Ust.-IdNr.
VAT Registration No.: DE129385895
Citibank Frankfurt (BLZ 502 109 00) 600119052
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
^ permalink raw reply [flat|nested] 7+ messages in thread* [tip:perfcounters/core] x86, perf_counter, bts: Correct pointer-to-u64 casts
2009-09-02 14:04 ` [patch 2/3] x86, perf_counter, bts: correct pointer-to-u64 casts markus.t.metzger
@ 2009-09-04 7:58 ` tip-bot for markus.t.metzger@intel.com
0 siblings, 0 replies; 7+ messages in thread
From: tip-bot for markus.t.metzger@intel.com @ 2009-09-04 7:58 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, a.p.zijlstra, markus.t.metzger, tglx,
mingo
Commit-ID: 596da17f94c103348ebe04129c00d536ea0e80e2
Gitweb: http://git.kernel.org/tip/596da17f94c103348ebe04129c00d536ea0e80e2
Author: markus.t.metzger@intel.com <markus.t.metzger@intel.com>
AuthorDate: Wed, 2 Sep 2009 16:04:47 +0200
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 4 Sep 2009 09:26:39 +0200
x86, perf_counter, bts: Correct pointer-to-u64 casts
On 32bit, pointers in the DS AREA configuration are cast to
u64. The current (long) cast to avoid compiler warnings results
in a signed 64bit address.
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <20090902140615.305889000@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/cpu/perf_counter.c | 24 ++++++++++++------------
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 2f41874..3776b0b 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -726,7 +726,8 @@ static inline void init_debug_store_on_cpu(int cpu)
return;
wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
- (u32)((u64)(long)ds), (u32)((u64)(long)ds >> 32));
+ (u32)((u64)(unsigned long)ds),
+ (u32)((u64)(unsigned long)ds >> 32));
}
static inline void fini_debug_store_on_cpu(int cpu)
@@ -757,7 +758,7 @@ static void release_bts_hardware(void)
per_cpu(cpu_hw_counters, cpu).ds = NULL;
- kfree((void *)(long)ds->bts_buffer_base);
+ kfree((void *)(unsigned long)ds->bts_buffer_base);
kfree(ds);
}
@@ -788,7 +789,7 @@ static int reserve_bts_hardware(void)
break;
}
- ds->bts_buffer_base = (u64)(long)buffer;
+ ds->bts_buffer_base = (u64)(unsigned long)buffer;
ds->bts_index = ds->bts_buffer_base;
ds->bts_absolute_maximum =
ds->bts_buffer_base + BTS_BUFFER_SIZE;
@@ -1491,7 +1492,7 @@ static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc,
};
struct perf_counter *counter = cpuc->counters[X86_PMC_IDX_FIXED_BTS];
unsigned long orig_ip = data->regs->ip;
- u64 at;
+ struct bts_record *at, *top;
if (!counter)
return;
@@ -1499,19 +1500,18 @@ static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc,
if (!ds)
return;
- for (at = ds->bts_buffer_base;
- at < ds->bts_index;
- at += sizeof(struct bts_record)) {
- struct bts_record *rec = (struct bts_record *)(long)at;
+ at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
+ top = (struct bts_record *)(unsigned long)ds->bts_index;
- data->regs->ip = rec->from;
- data->addr = rec->to;
+ ds->bts_index = ds->bts_buffer_base;
+
+ for (; at < top; at++) {
+ data->regs->ip = at->from;
+ data->addr = at->to;
perf_counter_output(counter, 1, data);
}
- ds->bts_index = ds->bts_buffer_base;
-
data->regs->ip = orig_ip;
data->addr = 0;
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [patch 3/3] x86, perf_counter, bts: do not allow kernel BTS tracing.
2009-09-02 14:04 [patch 0/3] x86, perf_counter, bts: incorporate review feedback and fix bugs markus.t.metzger
2009-09-02 14:04 ` [patch 1/3] x86, perf_counter, bts: fail if BTS is not available markus.t.metzger
2009-09-02 14:04 ` [patch 2/3] x86, perf_counter, bts: correct pointer-to-u64 casts markus.t.metzger
@ 2009-09-02 14:04 ` markus.t.metzger
2009-09-04 7:58 ` [tip:perfcounters/core] x86, perf_counter, bts: Do not allow kernel BTS tracing for now tip-bot for markus.t.metzger@intel.com
2 siblings, 1 reply; 7+ messages in thread
From: markus.t.metzger @ 2009-09-02 14:04 UTC (permalink / raw)
To: mingo, tglx, hpa
Cc: markus.t.metzger, a.p.zijlstra, linux-kernel, Peter Zijlstra,
Markus Metzger
[-- Attachment #1: tip.master.perf_counter.disable_kernel_bts.patch --]
[-- Type: text/plain, Size: 1074 bytes --]
Kernel BTS tracing generates too much data too fast for us to handle,
causing the kernel to hang.
Fail for BTS requests for kernel code.
CC: Peter Zijlstra <a.p.zjilstra@chello.nl>
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
---
arch/x86/kernel/cpu/perf_counter.c | 11 9 + 2 - 0 !
1 files changed, 9 insertions(+), 2 deletions(-)
Index: b/arch/x86/kernel/cpu/perf_counter.c
===================================================================
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -984,8 +984,15 @@ static int __hw_perf_counter_init(struct
* Branch tracing:
*/
if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
- (hwc->sample_period == 1) && !bts_available())
- return -EOPNOTSUPP;
+ (hwc->sample_period == 1)) {
+ /* BTS is not supported by this architecture. */
+ if (!bts_available())
+ return -EOPNOTSUPP;
+
+ /* BTS is currently only allowed for user-mode. */
+ if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
+ return -EOPNOTSUPP;
+ }
hwc->config |= config;
--
[-- Attachment #2: Type: text/plain, Size: 656 bytes --]
---------------------------------------------------------------------
Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/Muenchen Germany
Sitz der Gesellschaft: Feldkirchen bei Muenchen
Geschaeftsfuehrer: Douglas Lusk, Peter Gleissner, Hannes Schwaderer
Registergericht: Muenchen HRB 47456 Ust.-IdNr.
VAT Registration No.: DE129385895
Citibank Frankfurt (BLZ 502 109 00) 600119052
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
^ permalink raw reply [flat|nested] 7+ messages in thread* [tip:perfcounters/core] x86, perf_counter, bts: Do not allow kernel BTS tracing for now
2009-09-02 14:04 ` [patch 3/3] x86, perf_counter, bts: do not allow kernel BTS tracing markus.t.metzger
@ 2009-09-04 7:58 ` tip-bot for markus.t.metzger@intel.com
0 siblings, 0 replies; 7+ messages in thread
From: tip-bot for markus.t.metzger@intel.com @ 2009-09-04 7:58 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, markus.t.metzger, a.p.zjilstra, tglx,
mingo
Commit-ID: 1653192f510bd8114b7b133d7289e6e5c3e95046
Gitweb: http://git.kernel.org/tip/1653192f510bd8114b7b133d7289e6e5c3e95046
Author: markus.t.metzger@intel.com <markus.t.metzger@intel.com>
AuthorDate: Wed, 2 Sep 2009 16:04:48 +0200
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 4 Sep 2009 09:26:40 +0200
x86, perf_counter, bts: Do not allow kernel BTS tracing for now
Kernel BTS tracing generates too much data too fast for us to
handle, causing the kernel to hang.
Fail for BTS requests for kernel code.
Signed-off-by: Markus Metzger <markus.t.metzger@intel.com>
Acked-by: Peter Zijlstra <a.p.zjilstra@chello.nl>
LKML-Reference: <20090902140616.901253000@intel.com>
[ This is really a workaround - but we want BTS tracing in .32
so make sure we dont regress. The lockup should be fixed
ASAP. ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/cpu/perf_counter.c | 11 +++++++++--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 3776b0b..f9cd084 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -984,8 +984,15 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
* Branch tracing:
*/
if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
- (hwc->sample_period == 1) && !bts_available())
- return -EOPNOTSUPP;
+ (hwc->sample_period == 1)) {
+ /* BTS is not supported by this architecture. */
+ if (!bts_available())
+ return -EOPNOTSUPP;
+
+ /* BTS is currently only allowed for user-mode. */
+ if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
+ return -EOPNOTSUPP;
+ }
hwc->config |= config;
^ permalink raw reply related [flat|nested] 7+ messages in thread