From: Arjan van de Ven <arjan@infradead.org>
To: Luming Yu <luming.yu@gmail.com>
Cc: LKML <linux-kernel@vger.kernel.org>, Len Brown <lenb@kernel.org>,
"Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>,
"Siddha, Suresh B" <suresh.b.siddha@intel.com>
Subject: Re: [RFC PATCH] C2 could be mapped to C3 so need a flush cache
Date: Tue, 8 Sep 2009 01:32:40 -0700 [thread overview]
Message-ID: <20090908013240.51e39d1e@infradead.org> (raw)
In-Reply-To: <3877989d0909080120w78fce005le465828a5e1ae2b7@mail.gmail.com>
On Tue, 8 Sep 2009 16:20:52 +0800
Luming Yu <luming.yu@gmail.com> wrote:
> > Do you have an example of a specific machine where this is fscked
> > up? (if so, it's blacklist worthy.. probably worth blacklisting just
> > outright doing C states on it)
>
> Those boxes that have c2 lapic timer stop issue is supposed to need
> this patch. But I don't have such kind of system. So test and
> comments are needed by those who actually have such kind of box.
I find that highly unlikely; this software cache flush codepath hasn't
applied to any CPU sold in the last few years....
--
Arjan van de Ven Intel Open Source Technology Centre
For development, discussion and tips for power savings,
visit http://www.lesswatts.org
next prev parent reply other threads:[~2009-09-08 8:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-09-08 2:26 [RFC PATCH] C2 could be mapped to C3 so need a flush cache Luming Yu
2009-09-08 3:49 ` Arjan van de Ven
2009-09-08 5:09 ` Luming Yu
2009-09-08 7:52 ` Arjan van de Ven
2009-09-08 8:20 ` Luming Yu
2009-09-08 8:32 ` Arjan van de Ven [this message]
2009-09-08 15:38 ` Len Brown
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