From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Dave Jones <davej@redhat.com>
Cc: Linux Kernel <linux-kernel@vger.kernel.org>
Subject: Re: [X86] PCI: Use generic cacheline sizing instead of per-vendor tests.
Date: Wed, 14 Oct 2009 14:30:54 -0700 [thread overview]
Message-ID: <20091014143054.76874f30@jbarnes-g45> (raw)
In-Reply-To: <20091014203139.GA2336@redhat.com>
On Wed, 14 Oct 2009 16:31:39 -0400
Dave Jones <davej@redhat.com> wrote:
> Instead of the PCI code needing to have code to determine the
> cacheline size of each processor, use the data the cpu identification
> code should have already determined during early boot.
>
> (The vendor checks are also incomplete, and don't take into account
> modern CPUs)
>
> I've been carrying a variant of this code in Fedora for a while,
> that prints debug information. There are a number of cases where we
> are currently setting the PCI cacheline size to 32 bytes, when the CPU
> cacheline size is 64 bytes. With this patch, we set them both the
> same.
>
> Signed-off-by: Dave Jones <davej@redhat.com>
>
Does this improve performance enough to warrant putting it into the
current cycle? Or is queuing it for 2.6.33 sufficient?
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
next prev parent reply other threads:[~2009-10-14 21:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-14 20:31 [X86] PCI: Use generic cacheline sizing instead of per-vendor tests Dave Jones
2009-10-14 21:30 ` Jesse Barnes [this message]
2009-10-14 21:37 ` Dave Jones
2009-10-15 0:51 ` Dave Jones
2009-10-26 20:39 ` Jesse Barnes
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