Re: [PATCH] x86: eliminate redundant/contradicting cache line size config options

[Nick Piggin <npiggin@suse.de>]

On Thu, Nov 19, 2009 at 07:59:58AM -0800, Arjan van de Ven wrote:
> On Thu, 19 Nov 2009 09:13:07 +0100
> Nick Piggin <npiggin@suse.de> wrote:
> > 
> > My other point was just this, but I don't care too much. But it is
> > worded pretty negatively. The key here is that increasing the value
> > too large tends to only cost a very small amount of size (and no
> > increase in cacheline foot print, only RAM). 
> 
> 128 has a pretty significant impact on TPC-C benchmarks.....
> it was the top issue until mainline fixed it to default to 64

Really? I'm surprised, how much was it?

AFAIKS, in any case that 128 byte alignment is used, cache footprint
should not increased on a 64B line system, over 64 byte alignment.

I do see a silly thing in slab code that does not build a 192 byte
kmalloc slab in the case L1 cache bytes is 128 (it should build the
slab for the possibility that we've booted on a 64 byte system).
That might be increasing memory footprint a bit. But I still don't
see that cache footprint should be increased.

TLB, perhaps, because of increased memory usage. But I would have
thought memory usage increase should be pretty miniscule.