[PATCH v2] x86, amd: Make check_c1e_idle explicit

[Andreas Herrmann <herrmann.der.user@googlemail.com>]

With current code c1e_idle() will try to access MSR 0xc0010055 for all
future AMD CPUs. But that MSR is not architectural. So it's wrong to
access the MSR unconditionally.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/kernel/process.c |   14 ++++++--------
 1 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index ea54ce8..1bf98b1 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -494,21 +494,19 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 }
 
 /*
- * Check for AMD CPUs, which have potentially C1E support
+ * Check for AMD CPUs, which potentially use SMI or hardware initiated C1E
  */
 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 {
 	if (c->x86_vendor != X86_VENDOR_AMD)
 		return 0;
 
-	if (c->x86 < 0x0F)
-		return 0;
-
-	/* Family 0x0f models < rev F do not have C1E */
-	if (c->x86 == 0x0f && c->x86_model < 0x40)
-		return 0;
+	if ((c->x86 == 0x0F && c->x86_model >= 0x40) ||
+	    (c->x86 == 0x10) ||
+	    (c->x86 == 0x11))
+		return 1;
 
-	return 1;
+	return 0;
 }
 
 static cpumask_var_t c1e_mask;
-- 
1.6.4.2