Re: [BISECTED] drm: random hang since 620f378 "drm: prune modes when ..."

[Arnd Bergmann <arnd@arndb.de>]

On Monday 21 December 2009 16:06:43 Arnd Bergmann wrote:
> 
> -       if (IS_G4X(dev)) {
> -               u16 gcfgc;
> -
> -               /* Adjust render clock... */
> -               pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
> -
> -               /* Down to minimum... */
> -               gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
> -               gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
> -
> -               pci_write_config_word(dev->pdev, GCFGC, gcfgc);
> -       } else if (IS_I965G(dev)) {
> +       if (IS_I965G(dev)) {
>                 u16 gcfgc;

This crashed again immediately, apparently because IS_I965G is a superset
of IS_G4X (that seems counterintuitive), but not it seems to run using
this modified version of the patch (half an hour so far).

	Arnd

--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3783,7 +3783,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 
-	if (IS_IRONLAKE(dev))
+	if (IS_IRONLAKE(dev) || IS_G4X(dev))
 		return;
 
 	if (!dev_priv->render_reclock_avail) {
@@ -3792,7 +3792,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
 	}
 
 	/* Restore render clock frequency to original value */
-	if (IS_G4X(dev) || IS_I9XX(dev))
+	if (IS_I9XX(dev))
 		pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
 	else if (IS_I85X(dev))
 		pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
@@ -3808,7 +3808,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 
-	if (IS_IRONLAKE(dev))
+	if (IS_IRONLAKE(dev) || IS_G4X(dev))
 		return;
 
 	if (!dev_priv->render_reclock_avail) {
@@ -3816,16 +3816,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
 		return;
 	}
 
-	if (IS_G4X(dev)) {
-		u16 gcfgc;
-
-		/* Adjust render clock... */
-		pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
-
-		/* Down to minimum... */
-		gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
-		gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
-	} else if (IS_I965G(dev)) {
+	if (IS_I965G(dev)) {
 		u16 gcfgc;
 
 		/* Adjust render clock... */