Re: [PATCH 1/3] x86, cacheinfo: Fix disabling of L3 cache indexes

[Borislav Petkov <bp@amd64.org>]

On Wed, Jan 20, 2010 at 03:04:46PM -0800, H. Peter Anvin wrote:
> On 01/19/2010 03:07 AM, Borislav Petkov wrote:
> >  
> > +static void __wbinvd(void *dummy)
> > +{
> > +	asm volatile("wbinvd" : : : "memory");
> > +}
> > +
> 
> [...]
> 
> > +	smp_call_function_single(cpu, __wbinvd, NULL, 1);
> 
> I really don't like this combination.
> 
> First of all, it's an asm version of an instruction we already have
> macros for.  This should probably just be wbinvd(), or *possibly*
> native_wbinvd(), although that would have to be justified -- especially
> since the preexisting code used wbinvd().

The preexisting code using wbinvd is a bug since wbinvd has to happen on
a core which contains the L3 cache whose indices(!) we disable.

But yeah, a wbinvd smp version is a bit problematic since
smp_call_function_* expects a function pointer which has a void *
argument but native_wbinvd() has no args. By the way, there's a similar
thing in <drivers/char/agp/intel-agp.c::do_wbinvd()>

> Second, it's pretty obvious that the only reason for this function at
> all is to provide a wrapper that can be passed to smp_call_function*().
>  It would be a lot cleaner to have a small function wbinvd_on_cpu(cpu)
> as a wrapper for the higher-order functionality.

Done, see my next patch series.

-- 
Regards/Gruss,
Boris.

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Advanced Micro Devices, Inc.
Operating Systems Research Center