[tip:x86/mm] x86: Use the generic page_is_ram()

tip-bot for Wu Fengguang
2010-02-02T01:02:36Z

Commit-ID: 13ca0fcaa33f6b1984c4111b6ec5df42689fea6f
Gitweb: http://git.kernel.org/tip/13ca0fcaa33f6b1984c4111b6ec5df42689fea6f
Author: Wu Fengguang <fengguang.wu@intel.com>
AuthorDate: Fri, 22 Jan 2010 11:21:05 +0800
Committer: H. Peter Anvin <hpa@zytor.com>
CommitDate: Mon, 1 Feb 2010 16:58:17 -0800

x86: Use the generic page_is_ram()

The generic resource based page_is_ram() works better with memory
hotplug/hotremove. So switch the x86 e820map based code to it.

CC: Andi Kleen <andi@firstfloor.org>
CC: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
CC: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
LKML-Reference: <20100122033004.470767217@intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
---
arch/x86/include/asm/page_types.h | 1 -
arch/x86/mm/ioremap.c | 21 ---------------------
2 files changed, 0 insertions(+), 22 deletions(-)

diff --git a/arch/x86/include/asm/page_types.h b/arch/x86/include/asm/page_types.h
index 642fe34..a667f24 100644
--- a/arch/x86/include/asm/page_types.h
+++ b/arch/x86/include/asm/page_types.h
@@ -40,7 +40,6 @@

#ifndef __ASSEMBLY__

-extern int page_is_ram(unsigned long pagenr);
extern int devmem_is_allowed(unsigned long pagenr);

extern unsigned long max_low_pfn_mapped;
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 30e068d..1bf9e08 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -24,27 +24,6 @@

#include "physaddr.h"

-int page_is_ram(unsigned long pagenr)
-{
- resource_size_t addr, end;
- int i;
-
- for (i = 0; i < e820.nr_map; i++) {
- /*
- * Not usable memory:
- */
- if (e820.map[i].type != E820_RAM)
- continue;
- addr = (e820.map[i].addr + PAGE_SIZE-1) >> PAGE_SHIFT;
- end = (e820.map[i].addr + e820.map[i].size) >> PAGE_SHIFT;
-
-
- if ((pagenr >= addr) && (pagenr < end))
- return 1;
- }
- return 0;
-}
-
/*
* Fix up the linear direct mapping of the kernel to avoid cache attribute
* conflicts.