Re: [RFC perf,x86] P4 PMU early draft

[Robert Richter <robert.richter@amd.com>]

On 08.02.10 21:45:04, Cyrill Gorcunov wrote:
> Hi all,
> 
> first of all the patches are NOT for any kind of inclusion. It's not
> ready yet. More likely I'm asking for glance review, ideas, criticism.
> 
> The main problem in implementing P4 PMU is that it has much more
> restrictions for event to MSR mapping. So to fit into current
> perf_events model I made the following:
> 
> 1) Event representation. P4 uses a tuple of ESCR+CCCR+COUNTER
>    as an "event". Since every CCCR register mapped directly to
>    counter itself and ESCR and CCCR uses only 32bits of their
>    appropriate MSRs, I decided to use "packed" config in
>    in hw_perf_event::config. So that upper 31 bits are ESCR
>    and lower 32 bits are CCCR values. The bit 64 is for HT flag.
> 
>    So the base idea here is to pack into 64bit hw_perf_event::config
>    as much info as possible.
> 
>    Due to difference in bitfields I needed to implement
>    hw_perf_event::config helper which unbind hw_perf_event::config field
>    from processor specifics and allow to use it in P4 PMU.

If we introduce model specific configuration, we should put more model
specific code in here and then remove

  u64             (*raw_event)(u64);

in struct x86_pmu.

> 3) I've started unbinding x86_schedule_events into per x86_pmu::schedule_events
>    and there I hit hardness in binding HT bit. Have to think...

Instead of implemting x86_pmu.schedule_events() you should rather
abstract x86_pmu_enable(). This will be much more flexible to
implement other model spcific features.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com